参数资料
型号: FDY101PZ
厂商: Fairchild Semiconductor
文件页数: 2/6页
文件大小: 0K
描述: MOSFET P-CH 20V 150MA SC-89
产品变化通告: Mold Compound Change 20/Aug/2008
产品目录绘图: SOT-523F, SC89-3
标准包装: 1
系列: PowerTrench®
FET 型: MOSFET P 通道,金属氧化物
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 20V
电流 - 连续漏极(Id) @ 25° C: 150mA
开态Rds(最大)@ Id, Vgs @ 25° C: 8 欧姆 @ 150mA,4.5V
Id 时的 Vgs(th)(最大): 1.5V @ 250µA
闸电荷(Qg) @ Vgs: 1.4nC @ 4.5V
输入电容 (Ciss) @ Vds: 100pF @ 10V
功率 - 最大: 446mW
安装类型: 表面贴装
封装/外壳: SC-89,SOT-490
供应商设备封装: SC-89-3
包装: 标准包装
产品目录页面: 1605 (CN2011-ZH PDF)
其它名称: FDY101PZDKR
Electrical Characteristics
T A = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ Max
Units
Off Characteristics
BV DSS
Drain–Source Breakdown
V GS = 0 V,
I D = – 250 μ A
– 20
V
Voltage
? BV DSS
? T J
Breakdown Voltage Temperature
Coefficient
I D = – 250 μ A, Referenced to 25 ° C
15
mV/ ° C
I DSS
I GSS
Zero Gate Voltage Drain Current
Gate–Body Leakage,
V DS = – 16 V,
V GS = ± 8 V,
V GS = 0 V
V DS = 0 V
–3
± 10
μ A
μ A
On Characteristics
(Note 2)
V GS(th)
Gate Threshold Voltage
V DS = V GS , I D = – 250 μ A
– 0.65
– 1.0
– 1.5
V
? V GS(th)
? T J
R DS(on)
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
I D = 250 μ A, Referenced to 25 ° C
V GS = – 4.5 V, I D = – 150 mA
V GS = – 2.5 V, I D = – 125 mA
–3
8
12
mV/ ° C
?
V GS = – 1.8 V, I D = – 100 mA
V GS = – 1.5 V , I D = – 30 mA
V GS = – 4.5 V, I D = – 150mA,
T J = 125 ° C
15
20
12
g FS
Forward Transconductance
V DS = – 5 V, I D = – 150 mA
0.7
S
Dynamic Characteristics
C iss
C oss
C rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V DS = – 10 V,
f = 1.0 MHz
V GS = 0 V,
100
30
15
pF
pF
pF
Switchin g Characteristics
(Note 2)
t d(on)
t r
t d(off)
t f
Q g
Q gs
Q gd
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
V DD = – 10 V, I D = – 0.5 A,
V GS = – 4.5 V, R GEN = 6 ?
V DS = – 10 V, I D = – 150 mA,
V GS = – 4.5 V
6
13
8
1
1.0
0.2
0.3
12
23
16
2
1.4
ns
ns
ns
ns
nC
nC
nC
Drain–Source Diode Characteristics and Maximum Ratings
V SD
Drain–Source Diode Forward
V GS = 0 V,
I S = – 150 mA (Note 2)
– 0.8
– 1.2
V
Voltage
t rr
Q rr
Diode Reverse Recovery Time
Diode Reverse Recovery Charge
I F = – 150 mA,
dI F /dt = 100 A/μs
11
2
ns
nC
Notes:
1. R θ JA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R θ JC is guaranteed by design while R θ CA is determined by the user's board design.
mounted on a 1in pad
FDY101PZ Rev A
a)
200°C/W when
of 2 oz copper
2
b) 280°C/W when mounted on a
minimum pad of 2 oz copper
Scale 1 : 1 on letter size paper
2 . Pulse Test: Pulse Width < 300 μ s,
Duty Cycle < 2.0%
3. The diode connected between the gate
and source serves only as protection
againts ESD. No gate overvoltage
rating is implied.
www.fairchildsemi.com
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