参数资料
| 型号： | FIN210ACMLX |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 2/17页 |
| 文件大小： | 0K |
| 描述： | IC SER/DES 10BIT 32-MLP |
| 标准包装： | 3,000 |
| 功能： | 串行器/解串器 |
| 输入类型： | LVCMOS |
| 输出类型： | 串行 |
| 输入数： | 10 |
| 输出数： | 1 |
| 电源电压： | 1.65 V ~ 3.6 V |
| 工作温度： | -30°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-MLP（5x5） |
| 包装： | 带卷 (TR) |
SC16IS741_1
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 29 April 2010
10 of 52
NXP Semiconductors
SC16IS741
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
7.4 Hardware reset, Power-On Reset (POR) and software reset
These three reset methods are identical and will reset the internal registers as indicated in
Table 4 summarizes the state of register.
[1]
Registers DLL, DLH, SPR, XON1, XON2, XOFF1, XOFF2 are not reset by the top-level reset signal
RESET, POR or Software Reset, that is, they hold their initialization values during reset.
Table 5 summarizes the state of registers after reset.
Table 4.
Register reset[1]
Register
Reset state
Interrupt Enable Register
all bits cleared
Interrupt Identification Register
bit 0 is set; all other bits cleared
FIFO Control Register
all bits cleared
Line Control Register
reset to 0001 1101 (0x1D)
Modem Control Register
all bits cleared
Line Status Register
bit 5 and bit 6 set; all other bits cleared
Modem Status Register
bits 0:3 cleared; bits 4:7 input signals
Enhanced Feature Register
all bits cleared
Receiver Holding Register
pointer logic cleared
Transmitter Holding Register
pointer logic cleared
Transmission Control Register
all bits cleared.
Trigger Level Register
all bits cleared.
Transmit FIFO level
reset to 0100 0000 (0x40)
Receive FIFO level
all bits cleared
Extra Feature Register
all bits cleared
Table 5.
Output signals after reset
Signal
Reset state
TX
HIGH
RTS
HIGH
IRQ
HIGH by external pull-up
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