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| 型号： | FL103M |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 12/14页 |
| 文件大小： | 0K |
| 描述： | IC PWM CTLR FLYBACK 8-SOIC |
| 标准包装： | 2,500 |
| 系列： | TRUECURRENT™ |
| 恒定电流： | 是 |
| 恒定电压： | 是 |
| 拓扑： | 交直流离线开关，反激式，PWM |
| 输出数： | 1 |
| 内部驱动器： | 无 |
| 类型 - 主要： | 通用 |
| 频率： | 33kHz，50kHz |
| 电源电压： | 8 V ~ 25 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SO |
| 包装： | 带卷 (TR) |
| 工作温度： | -40°C ~ 125°C |
is between normal output voltage (V O ) and 50% of
normal output voltage (V O ). The other is 33 kHz. When
drops under 50% of normal voltage (V O ). At that time,
protection. To avoid 33 kHz, V O should be designed
Pulse-by-Pulse Current Limit
When the current sensing voltage (V CS ) across the
current-sense resistor (R Sense ) of MOSFET (Q1)
exceeds the internal threshold of 0.8 V, the MOSFET
(Q1) is turned off for the remainder of switching cycle. In
normal operation, the pulse-by-pulse current limit is not
triggered because the peak current is limited by the
control loop.
Leading-Edge Blanking (LEB)
Each time the power MOSFET (Q1) switches on, a turn-
on spike occurs at the sense resistor (R Sense ). To avoid
premature termination of the switching pulse, a leading-
edge blanking time is built in. Conventional RC filtering
can be omitted. During this blanking period, the current-
limit comparator is disabled and cannot switch off the
gate driver.
Gate Output
The FL103 output stage is a fast totem-pole gate driver.
Cross conduction has been avoided to minimize heat
dissipation, increase efficiency, and enhance reliability.
The output driver is clamped by an internal 15 V Zener
diode to protect power MOSFET transistors against
undesired over-voltage gate signals.
Built-in Slope Compensation
The sensed voltage across the current-sense resistor is
used for Current Mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability and prevents sub-harmonic oscillations due to
peak-current mode control. The FL103 has a
synchronized, positive-slope ramp built-in at each
switching cycle.
Noise Immunity
Noise from the current sense or the control signal can
cause significant pulse-width jitter, particularly in
Continuous-Conduction Mode. While slope
compensation helps alleviate these problems, further
precautions should still be taken. Good placement and
layout practices should be followed. Avoiding long PCB
traces and component leads, locating compensation
and filter components near the FL103, and increasing
the power MOSFET gate resistance are advised.
Operation Area
Figure 24 shows operation area. FL103 has two
switching frequency (f S ) in Constant Current Mode. One
is 50 kHz. In this case, FL103 can be operated with best
condition for LED illumination. The output voltage range
N
N
the output voltage is dropped, by increased load and
decreasing the number of LEDs, the output voltage (V O )
N
V DD drops to near UVLO protection and triggers
N
with enough margin.
? 2012 Fairchild Semiconductor Corporation
Figure 24.
Operation Area
www.fairchildsemi.com
FL103 ? Rev. 1.0.2
12
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