参数资料
型号: FL7930CM
厂商: FAIRCHILD SEMICONDUCTOR CORP
元件分类: 稳压器
英文描述: 0.5 A POWER FACTOR CONTROLLER, 350 kHz SWITCHING FREQ-MAX, PDSO8
封装: MS-012AA, SOP-8
文件页数: 4/20页
文件大小: 1290K
代理商: FL7930CM
2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FL7930 Rev. 1.0.0
12
FL7930
Single-Stage
Flyback
and
Bou
ndary-Mode
PFC
Controller
for
Lighting
Applications Information
1. Startup
: Normally, supply voltage (VCC) of a PFC
block is fed from the additional power supply, which can
be called standby power. Without this standby power,
auxiliary winding for zero current detection can be used
as a supply source. Once the supply voltage of the PFC
block exceeds 12V, internal operation is enabled until
the voltage drops to 8.5V. If VCC exceeds VZ, 20mA
current is sinking from VCC.
Figure 25. Startup Circuit
2. INV Block
: Scaled-down voltage from the output is
the input for the INV pin. Many functions are embedded
based on the INV pin: transconductance amplifier,
output OVP comparator, and disable comparator.
For the output voltage control, a transconductance
amplifier is used instead of the conventional voltage
amplifier. The transconductance amplifier (voltage-
controlled current source) aids the implementation of
OVP and disable functions. The output current of the
amplifier changes according to the voltage difference of
the inverting and non-inverting input of the amplifier. To
cancel down the line input voltage effect on power factor
correction, effective control response of PFC block
should be slower than the line frequency. This conflicts
with the transient response of controller. Two-pole one-
zero type compensation may be used to meet both
requirements.
The OVP comparator shuts down the output drive block
when the voltage of the INV pin is higher than 2.675V
with 0.175V hysteresis. The disable comparator
disables operation when the voltage of the inverting
input is lower than 0.35V with 100mV hysteresis. An
external small-signal MOSFET can be used to disable
the IC. The IC operating current decreases to reduce
power consumption if the IC is disabled. Figure 27 is the
timing chart of the internal circuit near the INV pin when
rated-PFC output voltage is assumed at 390VDC and
VCC supply voltage is 15V.
Figure 26. Circuit Around INV Pin
Figure 27. Timing Chart for INV Block
3.
OVP
Pin
: Over-Voltage Protection (OVP) is
embedded by the information at the INV pin. That
information comes from the output through the voltage
dividing resistors. To scale down from high voltage to
low voltage, high resistance normally replaced with low
resistance. If the resistor of high resistance is damaged
and resistance is changed to high, INV pin information is
normal, but output voltage exceeds its rated output.
Once this occurs, output electrolytic capacitor may be
damaged. The FL3930B provides an additional OVP pin
that can be used to shut down the boost power stage
when output voltage exceeds the OVP level if the
resistors connected at the INV pin are damaged. To
prevent such a catastrophe, an additional OVP pin is
assigned to double check output voltage. The additional
OVP may be called second OVP, while INV pin OVP
can be called the first OVP. Since the two OVP
conditions are quite different, the protection recovery
modes are different.
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