参数资料
型号: FL7930CM
厂商: FAIRCHILD SEMICONDUCTOR CORP
元件分类: 稳压器
英文描述: 0.5 A POWER FACTOR CONTROLLER, 350 kHz SWITCHING FREQ-MAX, PDSO8
封装: MS-012AA, SOP-8
文件页数: 5/20页
文件大小: 1290K
代理商: FL7930CM
2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FL7930 Rev. 1.0.0
13
FL7930
Single-Stage
Flyback
and
Bou
ndary-Mode
PFC
Controller
for
Lighting
Once the first OVP triggers, switching stops immediately
and recovers switching when the output voltage is
decreased with a hysteresis. When the second OVP
triggers, switching can be recovered only when the VCC
supply voltage falls below VSTOP and builds up higher
than VSTART again and VOVP is lower than hysteresis. If
the second OVP is not used, the OVP pin must be
connected to the INV pin or to ground.
Figure 28. Comparison of First and Second OVP
Recovery Modes
4. RDY Output
: The FL7930C provides a PFC-ready
pin that can be used to trigger other power stages when
PFC output voltage reaches the proper level with
hysteresis. When the INV voltage is higher than 2.24V,
RDY out is triggered HIGH and lasts until the INV
voltage is lower than 2.051V. When input AC voltage is
quite high, for example 240VAC, PFC output voltage is
always higher than RDY threshold, regardless of boost
converter operation. In this case, the INV voltage is
already higher than 2.24V before PFC VCC touches
VSTART. After boost converter operation stops, RDY is
not pulled LOW because the INV voltage is higher than
the RDY threshold. When VCC of the PFC drops below
5V, RDY is pulled LOW even through PFC output
voltage is higher than threshold. The RDY pin output is
open-drain, so needs an external pull-up resistor to
supply the proper power source. The RDY pin output
remains floating until VCC is higher than 2V.
Figure 29. Two Cases of RDY Triggered HIGH
Figure 30. Two Cases of RDY Triggered LOW
5. Control Range Compensation
: On time is controlled
by the output voltage compensator. When input voltage
is high and load is light, the control range becomes
narrow compared to when input voltage is low. That
control range decrease is anti-proportional to the double
square of the input voltage. Thus, at high line, unwanted
burst operation can occur at light load and audible noise
may be generated from the boost inductor or inductor at
input filter. Unlike other converters, burst operation in
PFC block is not needed because the PFC block itself is
normally disabled in Standby Mode. To reduce
unwanted burst operation at light load, internal control
range compensation is implemented and no burst
operation occurs until 5% load at high line.
6. Zero-Current Detection
: Zero-Current Detection
(ZCD) generates the turn-on signal of the MOSFET
when the boost inductor current reaches zero using an
auxiliary winding coupled with the inductor. When the
power switch turns on, negative voltage is induced at the
auxiliary winding due to the opposite winding direction
(see Equation 1) and positive voltage is induced (see
Equation 2)
when the power switch turns off.
AC
IND
AUX
V
T
V
(1)
AC
PFCOUT
IND
AUX
V
T
V
(2)
where VAUX is the auxiliary winding voltage; TIND and
TAUX are boost inductor turns and auxiliary winding
turns, respectively; VAC is input voltage for PFC
converter; and VOUT_PFC is output voltage from the
PFC converter.
Figure 31. Circuit Near ZCD
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