参数资料
型号: FPF1320UCX
厂商: Fairchild Semiconductor
文件页数: 13/15页
文件大小: 0K
描述: IC ADVANCED POWER SWITCH 6-WLCSP
标准包装: 3,000
系列: IntelliMax™
类型: 高端开关
输出数: 1
Rds(开): 60 毫欧
内部开关:
电流限制: 1.5A
输入电压: 1.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 6-UFBGA,WLCSP
供应商设备封装: 6-WLCSP
包装: 带卷 (TR)
Operation and Application Description
The FPF1320 and FPF1321 are dual-input single-output
power multiplexer switches with controlled turn-on and
seamless power source transition. The core is a 50 m ?
P-channel MOSFET and controller capable of
functioning over a wide input operating range of 1.5 V to
5.5 V per channel. The EN and SEL pins are active-
HIGH, GPIO/CMOS-compatible input. They control the
state of the switch and input power source selection,
respectively. TRCB functionality blocks unwanted
reverse current during both ON and OFF states when
higher V OUT than V IN A or V IN B is applied. FPF1321 has a
65 ? output discharge path during off.
Input Capacitor
To limit the voltage drop on the input supply caused by
transient inrush current when the switch turns on into a
discharged load capacitor; a capacitor must be placed
between the V IN A or V IN B pins to the GND pin. At least
1 μF ceramic capacitor, C IN , placed close to the pins, is
usually sufficient. Higher-value C IN can be used to
reduce more the voltage drop.
Inrush Current
Inrush current occurs when the device is turned on.
Inrush current is dependent on output capacitance and
slew rate control capability, as expressed by:
Power Source Selection
Input power source selection can be controlled by the
SEL pin. When SEL is LOW, output is powered from
V IN A while SEL is HIGH, V IN B is powering output. The
SEL signal is ignored during device OFF.
Output Voltage Drop during Transition
Output voltage drop usually occurs during input power
source transition period from low voltage to high
voltage. The drop is highly dependent on output
capacitance and load current.
FPF1320/1 adopts an advanced break-before-make
control, which can result in minimized output voltage
drop during the transition time.
Output Capacitor
Capacitor C OUT of at least 1 μF is highly recommended
between the V OUT and GND pins to achieve minimized
output voltage drop during input power source transition.
This capacitor also prevents parasitic board inductance.
True Reverse-Current Blocking
The true reverse-current blocking feature protects the
input source against current flow from output to input
regardless of whether the load switch is on or off.
I INRUSH = C OUT ×
where:
V IN ? V INITIAL
t R
+ I LOAD
(1)
Board Layout
For best performance, all traces should be as short as
possible. To be most effective, the input and output
capacitors should be placed close to the device to
C OUT :
t R :
V IN :
Output capacitance;
Slew rate or rise time at V OUT ;
Input voltage, V IN A or V IN B;
minimize the effect that parasitic trace inductance on
normal and short-circuit operation. Wide traces or large
copper planes for power pins (V IN A, V IN B, V OUT and
GND) minimize the parasitic electrical effects and the
thermal impedance.
V INITIAL : Initial voltage at C OUT , usually GND; and
I LOAD :
Load current.
Higher inrush current causes higher input voltage drop,
depending on the distributed input resistance and input
capacitance. High inrush current can cause problems.
FPF1320/1 has a 130 μs of slew rate capability under
3.3 V IN at 1 μF of C OUT and 150 ? of R L so inrush
current and input voltage drop can be minimized.
? 2011 Fairchild Semiconductor Corporation
FPF1320 / FPF1321 ? Rev. 1.0.2
13
www.fairchildsemi.com
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