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参数资料
| 型号： | FQD3P50TM_F085 |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 1/8页 |
| 文件大小： | 0K |
| 描述： | MOSFET P-CH 500V 2.1A DPAK |
| 标准包装： | 2,500 |
| 系列： | QFET™ |
| FET 型： | MOSFET P 通道，金属氧化物 |
| FET 特点： | 标准 |
| 漏极至源极电压(Vdss)： | 500V |
| 电流 - 连续漏极(Id) @ 25° C： | 2.1A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 4.9 欧姆 @ 1.05A，10V |
| Id 时的 Vgs(th)（最大）： | 5V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 23nC @ 10V |
| 输入电容 (Ciss) @ Vds： | 660pF @ 25V |
| 功率 - 最大： | 2.5W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | TO-252-3，DPak（2 引线+接片），SC-63 |
| 供应商设备封装： | D-Pak |
| 包装： | 带卷 (TR) |
July 2013
FQD3P50
P-Channel QFET ? MOSFET
- 500 V, - 2.1 A, 4.9 ?
Description
This P -Channel enhancement mode power MOSFET is
produced using Fairchild Semiconductor ? ’s proprietary
planar stripe and DMOS technology. This advanced
MOSFET technology has been especially tailored to
reduce on-state resistance, and to provide superior
switching performance and high avalanche energy
strength. These devices are suitable for switched mode
power supplies, active power factor correction (PFC), and
electronic lamp ballasts.
D
Features
? - 2.1 A, - 500 V, R DS(on) = 4.9 ? (Max.) @ V GS = - 10 V ,
ID = - 1.05 A
? Low G ate C harge ( T yp . 18 nC)
? Low Crss ( T yp . 9.5 pF)
? 100% A valanche T ested
S
!
G
S
D-PAK
(TO252)
G !
●
●
? ▲
●
!
D
Absolute Maximum Ratings
T C = 25°C unless otherwise noted
Symbol
V DSS
Drain-Source Voltage
Parameter
FQD3P50
-500
Unit
V
I D
Drain Current
- Continuous (T C = 25°C)
- Continuous (T C = 100°C)
-2.1
-1.33
A
A
I DM
Drain Current
- Pulsed
(Note 1)
-8.4
A
V GSS
Gate-Source Voltage
± 30
V
E AS
I AR
E AR
dv/dt
P D
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (T A = 25°C) *
Power Dissipation (T C = 25°C)
- Derate above 25°C
(Note 2)
(Note 1)
(Note 1)
(Note 3)
250
-2.1
5.0
-4.5
2.5
50
0.4
mJ
A
mJ
V/ns
W
W
W/°C
T J , T STG
T L
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8 " from case for 5 seconds
-55 to +150
300
°C
°C
Thermal Characteristics
Symbol
R θ JC
R θ JA
R θ JA
Parameter
Thermal Resistance, Junction-to-Case , Max.
Thermal Resistance, Junction-to-Ambient , Max. *
Thermal Resistance, Junction-to-Ambient , Max.
FQD3P50
2.5
50
110
Unit
°C / W
°C / W
°C / W
* When mounted on the minimum pad size recommended (PCB Mount)
?2009 Fairchild Semiconductor Corporation
FQD3P50 Rev. C 1
www.fairchildsemi.com
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