Latch on CS active
This triggers the latch when CS goes active, irrespective of WT or OE. You might choose this setting if
your system has a very narrow WT active signal. Latching the addresses much earlier in the cycle may
make it possible to operate in a target that violates our MNIMUM Twp spec of 25ns.
It may also allow us to operate properly in a target that generates noise on the address lines while the
write cycle is in process. Once a write has started, it is illegal to change the address lines. Any noise on
the address lines during the write will corrupt one or more memory locations. Some targets will have
stable addresses just before the WT goes active, but generate noise right after or during the WT active.
Latching earlier in the cycle makes us immune to these violations.
DO NOT USE THIS SETTING IF YOUR TARGET PERMANENTLY GROUNDS (ENABLES) THE
CS SIGNAL.
You also would NOT want to use this setting if your target does burst reads to the emulator. This occurs
when the target asserts CS and OE and then does a sequence of ADDRESS – controlled reads without
releasing either CS or OE between each access. In this case, you could use the ‘LATCH on CS and NOT
OE’ setting.
Latch on CS and WT active (default)
This triggers the latch when we see BOTH CS active and WT active. This is the default setting. It is
appropriate in most cases.
Latch on CS and either WT or OE
This latches the addresses when CS is active AND EITHER WT or OE are active. This might be
appropriate if noise on the address lines is causing access time violations. ‘LATCH on CS ACTIVE’ is
another option if your target does not have its CS line grounded and it does not do burst-reads.
Latch on CS and NOT OE
This setting triggers the latch when CS goes active, but then RELEASES the address lines if it sees OE
go active. This allows us to do early latching if desired but still support targets that do burst-reads.
Latch Delay Enable
This option specifies IF (and how much) we delay actually freezing the address lines after a signal
triggers latching. Most address line noise occurs immediately after control signals activate or when the
emulator begins driving data back to the target. Being able to delay latching the address until after the
noise settles down makes it possible for us to be immune to it.
The default setting is Latch Delay is ENABLED and set to its minimum delay setting.
Latch BHE/BLE Enable
This option specifies that we should freeze the Byte Enable signals as well as the addresses. It is on by
default. Most targets do not drive BLE or BHE directly. The ACM-8 derives them from A0. The ACM-
16 forces them both active. The only time you might need to turn this option OFF is if you are using the
ACM-C module and your target needs to change the Byte Enable lines without release CS or the WT or
OE signals. This is conceivable but highly unlikely.
FlexROM III User’s Manual
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