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参数资料
型号： FS6370-01G-XTP
厂商： ON Semiconductor
文件页数： 14/28页
文件大小： 0K
描述： IC CLOCK GEN PLL EEPROM 16SOIC
标准包装： 3,000
类型： PLL 时钟发生器
PLL： 是
输入： 晶体
输出： CMOS
电路数： 1
比率 - 输入:输出： 1:4
差分 - 输入:输出： 无/无
频率 - 最大： 230MHz
除法器/乘法器： 是/无
电源电压： 3 V ~ 5.5 V
工作温度： 0°C ~ 70°C
安装类型： 表面贴装
封装/外壳： 16-SOIC（0.154"，3.90mm 宽）
供应商设备封装： 16-SOIC
包装： 带卷 (TR)
FS6370
Table 13: AC Timing Specifications
Parameter
Symbol
Conditions/Description
Clock
(MHz)
Min.
Typ.
Max.
Units
Overall
EEPROM Write Cycle Time
Twc
4
ms
VDD = 5.5 V
0.8
150
Output Frequency *
fO
VDD = 3.6 V
0.8
100
MHz
VDD = 5.5 V
40
230
VCO Frequency *
fVCO
VDD = 3.6 V
40
170
MHz
VCO Gain *
AVCO
400
MHz/V
LFTC bit = 0
7
Loop Filter Time Constant *
LFTC bit = 1
20
μs
VO = 0.5 V to 4.5 V; CL = 15pF
2.0
Rise Time *
tr
VO = 0.3 V to 3.0 V; CL = 15pF
2.1
ns
VO = 4.5 V to 0.5 V; CL = 15pF
1.8
Fall Time *
tf
VO = 3.0 V to 0.3 V; CL = 15pF
1.9
ns
Tristate Enable Delay *
tPZL, tPZH
1
8
ns
Tristate Disable Delay *
tPZL, tPZH
1
8
ns
Output active from power-up, RUN mode via PD pin
100
μs
Clock Stabilization Time *
tSTB
After last register is written, register program mode
1
ms
Divider Modulus
Feedback Divider
NF
See also Error! Reference source not found.
8
2047
Reference Divider
NR
1
255
Post Divider
NP
See also Error! Reference source not found.
1
50
Clock Output (PLL A clock via CLK_A pin)
Duty Cycle *
Ratio of pulse width (as measured from rising edge to next falling
edge at 2.5V) to one clock period
100
45
55
%
On rising edges 500s apart at 2.5V relative to an ideal clock,
CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPX=50, no other
PLLs active
100
45
Jitter, Long Term (
σ
y(τ)) *
Tj(LT)
On rising edges 500s apart at 2.5V relative to an ideal clock,
CL=15pF, =14.318MHz, NF=220, NR=63, NPX=50, all other
PLLs active (B=60MHz, C=40MHz, D=14.318MHz)
50
165
ps
From rising edge to the next rising edge at 2.5V, CL=15pF,
fXIN=14.318MHz, NF=220, NR=63, NPX=50, no other PLLs
active
100
110
Jitter, Period (peak-peak)
*
tj(ΔP)
From rising edge to the next rising edge at 2.5V, CL=15pF,
fXIN=14.318MHz, NF=220, NR=63, NPX=50, all other PLLs
active (B=60MHz, C=40MHz, D=14.318MHz)
50
390
ps
Clock Output (PLL B clock via CLK_B pin)
Duty Cycle *
Ratio of pulse width (as measured from rising edge to next falling
edge at 2.5V) to one clock period
100
45
55
%
On rising edges 500s apart at 2.5V relative to an ideal clock,
CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPX=50, no other
PLLs active
100
45
Jitter, Long Term (
σ
y(τ)) *
Tj(LT)
On rising edges 500s apart at 2.5V relative to an ideal clock,
CL=15pF, =14.318MHz, NF=220, NR=63, NPX=50, all other
PLLs active (A=50MHz, C=40MHz, D=14.318MHz)
60
75
ps
From rising edge to the next rising edge at 2.5V, CL=15pF,
fXIN=14.318MHz, NF=220, NR=63, NPX=50, no other PLLs
active
100
120
Jitter, Period (peak-peak)
*
tj(ΔP)
60
400
ps
From rising edge to the next rising edge at 2.5V, CL=15pF,
fXIN=14.318MHz, NF=220, NR=63, NPX=50, all other PLLs
active (A=50MHz, C=40MHz, D=14.318MHz)
Rev. 3 | Page 21 of 28 | www.onsemi.com
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参数描述
FS6377 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Programmable 3-PLL Clock Generator IC
FS6377-01 制造商:AMI 制造商全称:AMI 功能描述:Programmable 3-PLL Clock Generator IC
FS6377-01G 制造商:AMI 制造商全称:AMI 功能描述:Programmable 3-PLL Clock Generator IC
FS6377-01G-XTD 功能描述:时钟发生器及支持产品 I2C PROG 3-PLL CLK RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56
FS6377-01G-XTP 功能描述:时钟发生器及支持产品 I2C PROG 3-PLL CLK RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56
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