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参数资料
| 型号： | FSDM07652REWDTU |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 12/20页 |
| 文件大小： | 0K |
| 描述： | IC SWIT PWM GREEN CM HV TO220F |
| 标准包装： | 50 |
| 输出隔离： | 隔离 |
| 频率范围： | 60 ~ 72kHz |
| 输入电压： | 8 V ~ 20 V |
| 输出电压： | 650V |
| 功率（瓦特）： | 80W |
| 工作温度： | 25°C ~ 150°C |
| 封装/外壳： | TO-220-6 全封装，成形引线 |
| 供应商设备封装： | TO-220F-6L（成形） |
| 包装： | 管件 |
| 产品目录页面： | 1222 (CN2011-ZH PDF) |
Functional Description
1. Start-up : In previous generations of Fairchild Power
Switches (FPS?), the V CC pin had an external start-up
resistor to the DC input voltage line. In this generation,
the start-up resistor is replaced by an internal high-
voltage current source. At start-up, the internal high-
voltage current source supplies the internal bias and
charges the external capacitor (C vcc ) connected to the
V CC pin, as illustrated in Figure 17. When V CC reaches
12V, the FSDM0x65RE begins switching and the internal
high-voltage current source is disabled. The
FSDM0x65RE continues normal switching operation and
the power is supplied from the auxiliary transformer
winding unless V CC goes below the stop voltage of 8V.
V DC
C Vcc
2.1 Pulse-by-Pulse Current Limit : Because current-
mode control is employed, the peak current through the
SenseFET is limited by the inverting input of PWM
comparator (V FB *) as shown in Figure 18. Assuming that
the 0.9mA current source flows only through the internal
resistor (2.5R + R = 2.8k Ω ), the cathode voltage of diode
D2 is about 2.5V. Since D1 is blocked when the feedback
voltage (V FB ) exceeds 2.5V, the maximum voltage of the
cathode of D2 is clamped at this voltage, thus clamping
V FB *. Therefore, the peak value of the current through
the SenseFET is limited.
2.2 Leading Edge Blanking (LEB) : At the instant the
internal SenseFET is turned on, a high-current spike
occurs through the SenseFET, caused by primary-side
capacitance and secondary-side rectifier reverse
recovery. Excessive voltage across the R sense resistor
would lead to incorrect feedback operation in the current
mode PWM control. To counter this effect, the
FSDM0x65RE employs a leading-edge blanking (LEB)
circuit. This circuit inhibits the PWM comparator for a
short time (t LEB ) after the SenseFET is turned on.
V CC
V ref
V CC
3
6
V str
V O
H11A817A
V FB
C B
4
I delay
D1
I FB
D2
2.5R
OSC
SenseFET
I start
+
Gate
V fb *
R
driver
8V/12V
V CC good
Vref
KA431
-
Internal
Bias
V SD
OLP
R sense
FSDM0565RE Rev: 00
FSDM0565RE Rev: 00
Figure 18. Pulse-Width-Modulation (PWM) Circuit
Figure 17. Internal Start-up Circuit
3. Protection Circuit : The FSDM0x65RE has several
self-protective functions, such as overload protection
2. Feedback Control : FSDM0x65RE employs current-
mode control, as shown in Figure 18. An opto-coupler
(such as the H11A817A) and shunt regulator (such as
the KA431) are typically used to implement the feedback
network. Comparing the feedback voltage with the
voltage across the R sense resistor, plus an offset voltage,
makes it possible to control the switching duty cycle.
When the reference pin voltage of the shunt regulator
exceeds the internal reference voltage of 2.5V, the opto-
coupler LED current increases, pulling down the
feedback voltage and reducing the duty cycle. This event
typically occurs when the input voltage is increased or
the output load is decreased.
? 2006 Fairchild Semiconductor Corporation
FSDM0465RE, FSDM0565RE, FSDM07652RE Rev. 1.0.2
12
(OLP), over-voltage protection (OVP), and thermal
shutdown (TSD). Because these protection circuits are
fully integrated into the IC without external components,
the reliability is improved without increasing cost. Once a
fault condition occurs, switching is terminated and the
SenseFET remains off, which causes V CC to fall. When
V CC reaches the UVLO stop voltage of 8V, the protection
is reset and the internal high-voltage current source
charges the V CC capacitor via the V str pin. When V CC
reaches the UVLO start voltage of 12V, the
FSDM0x65RE resumes normal operation. In this
manner, the auto-restart can alternately enable and
disable the switching of the power SenseFET until the
fault condition is eliminated (see Figure 19).
www.fairchildsemi.com
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