参数资料
型号: FSEZ1216BNY
厂商: Fairchild Semiconductor
文件页数: 12/15页
文件大小: 0K
描述: IC PWM CTLR MOSFET 8-DIP
产品变化通告: Product Discontinuation 27/Feb/2012
标准包装: 59
输出隔离: 隔离
频率范围: 39kHz ~ 45kHz
输入电压: 5.5 V ~ 25 V
输出电压: 600V
功率(瓦特): 800mW
工作温度: -40°C ~ 105°C
封装/外壳: 8-DIP(0.300",7.62mm)
供应商设备封装: 8-DIP
包装: 管件
产品目录页面: 1222 (CN2011-ZH PDF)
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds of the FSEZ1216B
are fixed internally at 16V/5V. During startup, the hold-
up capacitor must be charged to 16V through the
startup resistor, so that the FSEZ1216B is enabled. The
hold-up capacitor continues to supply V DD until power
can be delivered from the auxiliary winding of the main
transformer. V DD must not drop below 5V during this
startup process. This UVLO hysteresis window ensures
that the hold-up capacitor is adequate to supply V DD
during startup.
V DD Over-Voltage Protection (OVP)
V DD OVP is built in to prevent damage due to over-
voltage conditions. When the voltage V DD exceeds 28V
due to abnormal conditions, PWM pulses are disabled
until the V DD voltage drops below the UVLO and then
startup again. Over-voltage conditions are usually
caused by open feedback loops.
Over-Temperature Protection (OTP)
The FSEZ1216B has a built-in temperature-sensing
circuit to shut down PWM output once the junction
temperature exceeds 140°C. While PWM output is shut
down, the V DD voltage gradually drops to the UVLO
? 2008 Fairchild Semiconductor Corporation
FSEZ1216B Rev. 1.0.0
12
voltage. Some of the FSEZ1216B’s internal circuits are
shut down, and V DD gradually starts increasing again.
When V DD reaches 16V, all the internal circuits including
the temperature-sensing circuit starts operating
normally. If the junction temperature is still higher than
140°C, the PWM controller is shut down immediately.
Built-In Slope Compensation
The sensed voltage across the current-sense resistor is
used for current-mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability and prevents sub-harmonic oscillations due to
peak-current-mode control. The FSEZ1216B has a
synchronized, positively-sloped ramp built-in at each
switching cycle.
Noise Immunity
Noise from the current sense or the control signal can
cause significant pulse-width jitter, particularly in
continuous-conduction mode. While slope
compensation helps alleviate these problems, further
precautions should still be taken. Good placement and
layout practices should be followed. Avoid long PCB
traces and component leads, locating compensation
and filter components near the FSEZ1216B.
www.fairchildsemi.com
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