参数资料
| 型号： | FSEZ1317WAMY |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 12/16页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PSR/PWM 7-SOIC |
| 标准包装： | 2,500 |
| 输出隔离： | 隔离 |
| 频率范围： | 47kHz ~ 53kHz |
| 输入电压： | 5.5 V ~ 23 V |
| 输出电压： | 700V |
| 工作温度： | -40°C ~ 105°C |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally at
16 V and 5 V, respectively. During startup, the hold-up
capacitor must be charged to 16V through the startup
resistor to enable the FSEZ1317WA. The hold-up
capacitor continues to supply V DD until power can be
delivered from the auxiliary winding of the main
transformer. V DD is not allowed to drop below 5 V during
this startup process. This UVLO hysteresis window
ensures that hold-up capacitor properly supplies V DD
during startup.
Protections
The FSEZ1317WA has several self-protection functions,
such as Over-Voltage Protection (OVP), Over-
Temperature Protection (OTP), and pulse-by-pulse
current limit. All the protections are implemented as
auto-restart mode. Once the abnormal condition occurs,
the switching is terminated and the MOSFET remains
off, causing V DD to drop. When V DD drops to the V DD
turn-off voltage of 5 V, internal startup circuit is enabled
again and the supply current drawn from the HV pin
charges the hold-up capacitor. When V DD reaches the
turn-on voltage of 16 V, normal operation resumes. In
this manner, the auto-restart alternately enables and
disables the switching of the MOSFET until the
abnormal condition is eliminated (see Figure 29).
Over-Temperature Protection (OTP)
The built-in temperature-sensing circuit shuts down
PWM output if the junction temperature exceeds 140°C.
Pulse-by-pulse Current Limit
When the sensing voltage across the current-sense
resistor exceeds the internal threshold of 0.8 V, the
MOSFET is turned off for the remainder of switching
cycle. In normal operation, the pulse-by-pulse current
limit is not triggered since the peak current is limited by
the control loop.
Leading-Edge Blanking (LEB)
Each time the power MOSFET switches on, a turn-on
spike occurs at the sense resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period,
the current-limit comparator is disabled and cannot
switch off the gate driver. As a result conventional RC
filtering can be omitted.
Gate Output
The FSEZ1317WA output stage is a fast totem-pole
gate driver. Cross conduction has been avoided to
minimize heat dissipation, increase efficiency, and
enhance reliability. The output driver is clamped by an
internal 15 V Zener diode to protect the power MOSFET
transistors against undesired over-voltage gate signals.
Built-In Slope Compensation
The sensed voltage across the current-sense resistor is
used for current mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability and prevents sub-harmonic oscillations due to
peak-current mode control. The FSEZ1317WA has a
synchronized, positive-slope ramp built-in at each
switching cycle.
Noise Immunity
Noise from the current sense or the control signal can
cause significant pulsewidth jitter, particularly in
continuous-conduction mode. While slope
compensation helps alleviate these problems, further
precautions should still be taken. Good placement and
layout practices should be followed. Avoiding long PCB
traces and component leads, locating compensation
and filter components near the FSEZ1317WA, and
increasing the power MOS gate resistance are advised.
Figure 29. Auto-Restart Operation
V DD Over-Voltage Protection (OVP)
V DD over-voltage protection prevents damage from over-
voltage conditions. If the V DD voltage exceeds 24V at
open-loop feedback condition, OVP is triggered and the
PWM switching is disabled. The OVP has a debounce
time (typically 200 μs) to prevent false triggering due to
switching noises.
? 2012 Fairchild Semiconductor Corporation
FSEZ1317WA ? Rev. 1.0.2
12
www.fairchildsemi.com
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