参数资料
| 型号： | FSFM261N |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 10/18页 |
| 文件大小： | 0K |
| 描述： | IC PWM/SENSEFET FPS 8-DIP |
| 标准包装： | 50 |
| 系列： | FPS™ |
| 输出隔离： | 隔离 |
| 频率范围： | 61kHz ~ 73kHz |
| 输入电压： | 9 V ~ 21 V |
| 输出电压： | 700V |
| 功率（瓦特）： | 35W |
| 工作温度： | -25°C ~ 85°C |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-DIP |
| 包装： | 管件 |
R LIM ? I LIM _ SPEC
Functional Description
1. Startup : In previous generations of Fairchild Power
Switches (FPS?), the V CC pin had an external startup
resistor to the DC input voltage line. In this generation,
the startup resistor is replaced by an internal high-
voltage current source. At startup, an internal high-
values of 2.5V and 1.5A, respectively. The pulse-by-
pulse current limit can be adjusted using a resistor to
GND on the current limit pin (#4). The current limit level
using an external resistor (R LIM ) is given by:
I LIM = (1)
2 . 8 k Ω + R LIM
voltage current source supplies the internal bias and
charges the external capacitor (C vcc ) connected to the
V CC pin, as illustrated in Figure 16. When V CC reaches
=> R LIM =
I LIM ? 2 . 8 k Ω
I LIM _ SPEC ? I LIM
(2)
12V, the FSFM260/261/300 begins switching and the
internal high-voltage current source is disabled. Then,
where, I LIM is the desired drain current limit.
the FSFM260/261/300 continues its normal switching
operation and the power is supplied from the auxiliary
transformer winding unless V CC goes below the stop
voltage of 8V.
V DC
V O
FOD817A
Vfb
C B
3
V CC
I delay
D1
V CC
I FB
D2
+
V fb *
2.5R
R
OSC
SenseFET
Gate
driver
C Vcc
KA431
-
V SD
OLP
R sense
V CC
2
5
Vstr
FSFM260 Rev: 00
Figure 17. Pulse Width Modulation (PWM) Circuit
I start
2.2 Leading-Edge Blanking (LEB) : At the instant the
8V/12V
V CC good
Vref
internal SenseFET is turned on, a high-current spike
occurs through the SenseFET, caused by primary-side
capacitance and secondary-side rectifier reverse
Internal
Bias
FSFM260 Rev: 00
Figure 16. Internal Startup Circuit
2. Feedback Control : FSFM260/261/300 employs
current-mode control, as shown in Figure 17. An opto-
coupler (such as the FOD817A) and shunt regulator
(such as the KA431) are typically used to implement the
feedback network. Comparing the feedback voltage with
the voltage across the R SENSE resistor makes it possible
to control the switching duty cycle. When the reference
pin voltage of the shunt regulator exceeds the internal
reference voltage of 2.5V, the opto coupler LED current
increases, pulling down the feedback voltage and
reducing the duty cycle. This typically occurs when the
input voltage is increased or the output load is
decreased.
2.1 Pulse-by-Pulse Current Limit : Because current-
mode control is employed, the peak current through the
SenseFET is determined by the inverting input of the
PWM comparator (V FB *), as shown in Figure 17. When
recovery. Excessive voltage across the R SENSE resistor
would lead to incorrect feedback operation in the current-
mode PWM control. To counter this effect, the FSFM260/
261/300 employs a leading edge blanking (LEB) circuit.
This circuit inhibits the PWM comparator for a short time
(t LEB ) after the SenseFET is turned on.
2.3 Constant Power Limit Circuit : Due to the circuit
delay of FPS, the pulse-by-pulse limit current increases
a little bit when the input voltage increases. This means
unwanted excessive power is delivered to the secondary
side. To compensate, the auxiliary power compensation
network in Figure 18 can be used. R LIM can adjust pulse-
by-pulse current by absorbing internal current source
(I FB : typical value is 0.9mA) depending on the ratio
between resistors. With the suggested compensation
circuit, additional current from I FB is absorbed more
proportionally to the input voltage (V DC ) and achieves
constant power in wide input range. Choose R LIM for
proper current to the application, then check the pulse-
by-pulse current difference between minimum and
maximum input voltage. To eliminate the difference (to
gain constant power), R y can be calculated by:
I lim_spec × V dc ×
the current through the opto-transistor is zero and the
current limit pin (#4) is left floating, the feedback current
source (I FB ) of 0.9mA flows only through the internal
resistor (R+2.5R=2.8k). In this case, the cathode voltage
R y ?
I fb × Δ I lim_comp
N a
N p
(3)
of diode D2 and the peak drain current have maximum
? 2009 Fairchild Semiconductor Corporation
FSFM260N / FSFM261N / FSFM300N ? Rev. 1.0.1
10
www.fairchildsemi.com
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