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参数资料
| 型号： | FSH250300-1M |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 3000 MHz, QCC36 |
| 封装： | ROHS COMPLIANT, SMT-36 |
| 文件页数： | 1/2页 |
| 文件大小： | 373K |
| 代理商： | FSH250300-1M |
INTEGRATED FREQUENCY SYNTHESIZER
2500 - 3000 MHz
OPTIMIZED LOOP PARAMETERS
SURFACE MOUNT MODEL: FSH250300-1M
FEATURES:
Exceptionally Low Phase Noise
Optimized Reference Sidebands
Lead Free - RoHS Compliant
Patent Pending REL-PRO Technology
Small Size, Surface Mount
Phase Noise
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
100
1000
10000
100000
1000000
10000000
Offset Frequency (Hz)
Phase
Noise
(dB
c/Hz)
2500.00 MHz / 8.27 dBm
2750.00 MHz / 9.33 dBm
3000.00 MHz / 10.3 dBm
SPECIFICATIONS (Rev. B 10/02/06)
Frequency
2500 - 3000 MHz
Step Size
10 MHz
Reference
Input Frequency
10 MHz *
Reference
Input Voltage
1 V p-p to 3.3 V p-p
Bias Voltage
Vcc
V (Vdc) I (mA Max.)
Digital
+5
50
VCO
+10
40
Tune
+24
50
Output Power
+8 dBm (Min.)
VSWR
1.8:1 (Typ.)
Spurious Suppression
-90 dBc (Typ.)
Harmonic Suppression
-25 dBc (Typ.)
Settling Time
15 mSec (Typ.) **
Output Impedance
50 Ohms (Nom.)
Typical Phase Noise
Offset
Phase Noise
@ 1 kHz
-95 dbc/Hz
@ 10 kHz
-98 dbc/Hz
@ 100 kHz
-122 dbc/Hz
Operating
Temperature Range
-40 to +85 °C
Programming
See Application Note: AN7100
* Reference input frequency is programmable in multiples of the step
size. 10 MHz is the default setting.
** From the rising edge of LE to stable lock detect
Package #
197LF
PIN-OUT
Pin 5 - RF Out
Pin 7 - Lock Detect Out
Pin 9 - Data In
Pin 10 - Error Flag
Pin 11 - Clock In
Pin 16 - Reset
Pin 19 - Latch Enable In
Pin 21 - Ref. In
Pin 23 - Vcc (Digital)
Pin 24 - Vtune Out
Pin 25 - Vcc (VCO)
Pin 27 - Vcc (Tune)
Pin 8,12,13,14 - NC
Pin 15,17,26,28 - NC
All Others - Ground
NC - No Connection
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