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参数资料
| 型号： | FSHDMI08MTD |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 8/11页 |
| 文件大小： | 0K |
| 描述： | IC HDMI SWITCH DDC/CEC 56-TSSOP |
| 标准包装： | 34 |
| 功能： | 开关，DVI/HDMI |
| 电路： | 3 x 2:1 |
| 电压电源： | 单电源 |
| 电压 - 电源，单路/双路(±)： | 3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 56-TSSOP |
| 包装： | 管件 |
Micrel, Inc.
SY54017R
March 2008
6
M9999-033108-A
hbwhelp@micrel.com or (408) 955-1690
AC Electrical Characteristics
VCCO = 1.14V to 1.26V RL = 50 to VCCO, VCCO = 1.7V to 1.9V, RL = 50 to VCCO or 100 across the outputs,
VCC = 2.375V to 2.625V. TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
NRZ Data
3.2
Gbps
fMAX
Maximum Frequency
VOUT > 200mV
Clock
2.5
GHz
VIN: 100mV-200mV, Note 6, Figure 1a
220
320
470
ps
VIN: >200mV, Note 6, Figure 1a
190
270
390
ps
tPD
Propagation Delay
IN-to-Q
SEL-to-Q
See Figure 1a
90
200
350
ps
Input-to-Input Skew
Note 8
5
20
ps
tSkew
Part-to-Part Skew
Note 9
75
ps
Note 10
1
psRMS
Data
Random Jitter
Deterministic Jitter
Note 11
10
psPP
Note 12
1
psRMS
Note 13
10
psPP
tJitter
Clock
Cycle-to-Cycle Jitter
Total Jitter
Crosstalk Induced Jitter
(Adjacent Channel)
Note 14
0.7
psPP
tR tF
Output Rise/Fall Times
(20% to 80%)
At full output swing.
30
60
95
ps
Duty Cycle
Differential I/O
47
53
%
Notes:
6.
Propagation delay is measured with input tr/tf ≤300ps (20% to 80%).
8.
Input-to-Input skew is the difference in time between both inputs and the output for the same temperature, voltage and transition.
9.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs. Vin >200mV with input tr/tf ≤300ps (20% to 80%).
10. Random jitter is measured with a K28.7 pattern, measured at
≤ f
MAX.
11. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2
23–1 PRBS pattern.
12. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn –Tn+1,
where T is the time between rising edges of the output signal.
13. Total jitter definition: with an ideal clock input frequency of
≤ f
MAX (device), no more than one output edge in 10
12 output edges will deviate by
more than the specified peak-to-peak jitter value.
14. Crosstalk induced jitter is defined as the added jitter that results from signals applied to the adjacent channel. It is measured at the output while
applying a similar, differential clock frequencies that are asynchronous with respect to each other at the adjacent input.
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