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| 型号： | FSQ0765RQUDTU |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 12/19页 |
| 文件大小： | 0K |
| 描述： | IC CONV QUASI-RES 650V TO-220F-6 |
| 标准包装： | 400 |
| 输出隔离： | 隔离 |
| 频率范围： | 48kHz ~ 67kHz |
| 输入电压： | 9 V ~ 20 V |
| 输出电压： | 650V |
| 功率（瓦特）： | 90W |
| 工作温度： | -25°C ~ 85°C |
| 封装/外壳： | TO-220-6 成形引线 |
| 供应商设备封装： | TO-220-6L（成形） |
| 包装： | 管件 |
Functional Description
1. Startup: At startup, an internal high-voltage current
source supplies the internal bias and charges the
external capacitor (C a ) connected to the V CC pin, as
illustrated in Figure 22. When V CC reaches 12V, the
FPS? begins switching and the internal high-voltage
current source is disabled. The FPS continues its normal
switching operation and the power is supplied from the
auxiliary transformer winding unless V CC goes below the
stop voltage of 8V.
2.2 Leading-Edge Blanking (LEB): At the instant the
internal SenseFET is turned on, a high-current spike
usually occurs through the SenseFET, caused by
primary-side capacitance and secondary-side rectifier
reverse recovery. Excessive voltage across the R sense
resistor would lead to incorrect feedback operation in the
current-mode PWM control. To counter this effect, the
FPS employs a leading-edge blanking (LEB) circuit. This
circuit inhibits the PWM comparator for a short time
(t LEB ) after the SenseFET is turned on.
V DC
V CC
I delay
V ref
I FB
C a
V O
FOD817A
V FB
C B
4
D1
D2
3R
OSC
SenseFET
+
V FB *
R
Gate
driver
3
V CC
I CH
6
V str
KA431
V SD
-
OLP
R sense
8V/12V
V CC good
V ref
FSQ0765R Rev. 00
Figure 23. Pulse-Width-Modulation (PWM) Circuit
Internal
FSQ0765R Rev.00
Bias
3. Synchronization: The FSQ-series employs a quasi-
resonant switching technique to minimize the switching
Figure 22. Startup Circuit
2. Feedback Control: FPS employs current-mode
control, as shown in Figure 23. An opto-coupler (such as
the FOD817A) and shunt regulator (such as the KA431)
are typically used to implement the feedback network.
Comparing the feedback voltage with the voltage across
the R sense resistor makes it possible to control the
switching duty cycle. When the reference pin voltage of
noise and loss. The basic waveforms of the quasi-
resonant converter are shown in Figure 24. To minimize
the MOSFET's switching loss, the MOSFET should be
turned on when the drain voltage reaches its minimum
value, which is indirectly detected by monitoring the V CC
winding voltage, as shown in Figure 24.
V ds
V RO
the shunt regulator exceeds the internal reference
voltage of 2.5V, the opto-coupler LED current increases,
pulling down the feedback voltage and reducing the duty
cycle. This typically happens when the input voltage is
increased or the output load is decreased.
V sync
V DC
t F
V RO
V ovp (8V)
2.1 Pulse-by-Pulse Current Limit: Because current-
mode control is employed, the peak current through the
SenseFET is limited by the inverting input of PWM
comparator (V FB *), as shown in Figure 23. Assuming
that the 0.9mA current source flows only through the
internal resistor (3R + R = 2.8k), the cathode voltage of
diode D2 is about 2.5V. Since D1 is blocked when the
feedback voltage (V FB ) exceeds 2.5V, the maximum
voltage of the cathode of D2 is clamped at this voltage,
MOSFET Gate
ON
1.2V
1.0V
230ns Delay
ON
clamping V FB *. Therefore, the peak value of the current
through the SenseFET is limited.
? 2008 Fairchild Semiconductor Corporation
FSQ0765RQ Rev. 1.0.1
12
FSQ0765R Rev.00
Figure 24. Quasi-Resonant Switching Waveforms
www.fairchildsemi.com
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