参数资料
型号: FSQ0765RQUDTU
厂商: Fairchild Semiconductor
文件页数: 15/19页
文件大小: 0K
描述: IC CONV QUASI-RES 650V TO-220F-6
标准包装: 400
输出隔离: 隔离
频率范围: 48kHz ~ 67kHz
输入电压: 9 V ~ 20 V
输出电压: 650V
功率(瓦特): 90W
工作温度: -25°C ~ 85°C
封装/外壳: TO-220-6 成形引线
供应商设备封装: TO-220-6L(成形)
包装: 管件
uses a sync signal instead of directly monitoring the
output voltage. If the sync signal exceeds 8V, an OVP is
triggered, shutting down the SMPS. To avoid undesired
triggering of OVP during normal operation, there are two
points to be considered, which are depicted in Figure 32.
One is at the peak voltage of the sync signal should be
designed below 6V and the other is that the spike of the
sync pin should be as low as possible; not to get longer
than t OVP by decreasing the leakage inductance shown
at V CC winding coil.
6. Burst Operation: To minimize power dissipation in
standby mode, the FPS enters burst-mode operation. As
the load decreases, the feedback voltage decreases. As
shown in Figure 33, the device automatically enters
burst-mode when the feedback voltage drops below
V BURL (350mV). At this point, switching stops and the
output voltages start to drop at a rate dependent on
standby current load. This causes the feedback voltage
to rise. Once it passes V BURH (550mV), switching
resumes. The feedback voltage then falls and the
V Vcc_coil & V CC
V CC
Absolue max V CC (20V)
V Vcc_coil
FSQ0765R Rev.00
process repeats. Burst-mode operation alternately
enables and disables switching of the power SenseFET,
thereby reducing switching loss in standby mode.
V O
V Oset
V sync
Improper OVP triggering
V OVP (8V)
V DC
N pri
N Vcc
V FB
0.55V
0.35V
I DS
t OVP
V SH2 (4.8V)
V CLAMP
t OVP
V DS
Figure 32. OVP Triggering
time
4.5 Thermal Shutdown with Hysteresis (TSD): The
SenseFET and the control IC are built in one package.
FSQ0765R Rev.00
t1
Switching
disabled
t2 t3
Switching
disabled
t4
This allows the control IC to detect abnormally high
temperature of the SenseFET. If the temperature
exceeds approximately 140°C, the thermal shutdown
triggers IC shutdown. The IC recovers its operation when
the junction temperature decreases 60°C from TSD
temperature and V CC reaches startup voltage (V start ).
5. Soft-Start: The FPS has an internal soft-start circuit
that increases PWM comparator inverting input voltage
with the SenseFET current slowly after it starts up. The
typical soft-start time is 17.5ms. The pulse width to the
power switching device is progressively increased to
establish the correct working conditions for transformers,
inductors, and capacitors. The voltage on the output
capacitors is progressively increased with the intention of
smoothly establishing the required output voltage. This
mode helps prevent transformer saturation and reduces
stress on the secondary diode during startup.
? 2008 Fairchild Semiconductor Corporation
FSQ0765RQ Rev. 1.0.1
15
Figure 33. Waveforms of Burst Operation
7. Switching Frequency Limit: To minimize switching
loss and Electromagnetic Interference (EMI), the
MOSFET turns on when the drain voltage reaches its
minimum value in quasi-resonant operation. However,
this causes switching frequency to increases at light load
conditions. As the load decreases or input voltage
increases, the peak drain current diminishes and the
switching frequency increases. This results in severe
switching losses at light-load condition, as well as
intermittent switching and audible noise. These problems
create limitations for the quasi-resonant converter
topology in a wide range of applications.
To overcome these problems, FSQ-series employs a
frequency-limit function, as shown in Figures 34 and 35.
Once the SenseFET is turned on, the next turn-on is
prohibited during the blanking time (t B ). After the
blanking time, the controller finds the valley within the
detection time window (t W ) and turns on the MOSFET, as
shown in Figures 34 and Figure 35 (Cases A, B, and C).
www.fairchildsemi.com
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