参数资料
型号: FSQ100
厂商: Fairchild Semiconductor
文件页数: 8/12页
文件大小: 0K
描述: IC SWIT PWM GREEN OVP HV 8DIP
标准包装: 50
输出隔离: 隔离
频率范围: 61 ~ 73kHz
输入电压: 8 V ~ 20 V
输出电压: 650V
功率(瓦特): 8W
工作温度: 25°C ~ 145°C
封装/外壳: 8-DIP(0.300",7.62mm)
供应商设备封装: 8-DIP
包装: 管件
Functional Description
1. Startup : At startup, the internal high-voltage current
source supplies the internal bias and charges the
external V CC capacitor, as shown in Figure 14. When
V CC reaches 9V, the device starts switching and the
internal high-voltage current source stops charging the
capacitor. The device is in normal operation provided
V CC does not drop below 7V. After startup, the bias is
supplied from the auxiliary transformer winding.
When the shunt regulator reference pin voltage exceeds
the internal reference voltage of 2.5V, the opto-coupler
LED current increases, the feedback voltage V FB is
pulled down, and it reduces the duty cycle. This
happens when the input voltage increases or the output
load decreases.
V IN ,dc
V CC
V ref
OSC
V CC
L
I STR
Vstr
VO
Vfb
C fb
5μA
4
+
V fb
400μA
R
Gate
driver
H
KA431
V SD
OLP
9V/ 7V
Figure 16.
PWM and Feedback Circuit
Figure 14. Internal Startup Circuit
Calculating the V CC capacitor is an important step to
design with the FSQ100. At initial startup, the maximum
value of start operating current I START is about 100μA,
which supplies current to UVLO and V REF blocks. The
charging current I VCC of the V CC capacitor is equal to I STR
– 100μA. After V CC reaches the UVLO start voltage, only
the bias winding supplies V CC current to the device.
When the bias winding voltage is not sufficient, the V CC
level decreases to the UVLO stop voltage and the
internal current source is activated again to charge the
V CC capacitor. To prevent this V CC fluctuation
(charging/discharging), the V CC capacitor should be
chosen to have a value between 10μF and 47μF.
3. Leading Edge Blanking (LEB) : At the instant the
internal SenseFET is turned on, the primary-side
capacitance and secondary-side rectifier diode reverse
recovery typically causes a high-current spike through
the SenseFET. Excessive voltage across the R SENSE
resistor lead to incorrect pulse-by-pulse current limit
protection. To avoid this, a leading edge blanking (LEB)
circuit disables pulse-by-pulse current-limit protection
block for a fixed time (t LEB ) after the SenseFET turns on.
4. Protection Circuit : The FSQ100 has protective
functions, such as overload protection (OLP), over
voltage protection (OVP), under-voltage lockout (UVLO),
and thermal shutdown (TSD). Because these protection
circuits are fully integrated inside the IC without external
components, reliability is improved without increasing
V IN ,dc
I Vcc = I STR -I START
I Vcc = I STR -I START
V CC
I STR
I START
U VLO
V ref
V STR
J-FET
costs. Once a fault condition occurs, switching is
terminated and the SenseFET remains off. This causes
V CC to fall. When V CC reaches the UVLO stop voltage
V STOP (7V), the protection is reset and the internal high-
voltage current source charges the V CC capacitor via the
V STR pin. When V CC reaches the UVLO start voltage
V START (9V), the device resumes normal operation. In
this manner, the auto-restart can alternately enable and
disable the switching of the power SenseFET until the
fault condition is eliminated.
V CC
V START
UV LO
OSC
V STOP
V CC must not drop
below V STOP
Bias winding
voltage
V fb
4
5 μA
400μA
R
+
-
S Q
R
GATE
DRIVER
t
C fb
OLP
S Q
Figure 15.
Charging V CC Capacitor through Vstr
RESET
4.5V
TSD
A /R
R
OLP, TSD
Protection Block
2. Feedback Control : The FSQ100 is a voltage mode
controlled device, as shown in Figure 16. Usually, an
opto-coupler and shunt regulator, like KA431 are used
to implement the feedback network. The feedback
voltage is compared with an internally generated
sawtooth waveform. This directly controls the duty cycle.
Figure 17.
Protection Block
? 2007 Fairchild Semiconductor Corporation
FSQ100 Rev. 1.0.2
8
www.fairchildsemi.com
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