参数资料
型号: FT24C08A-USG-B
厂商: Fremont Micro Devices USA
文件页数: 3/20页
文件大小: 0K
描述: IC EEPROM 8KBIT 1MHZ 8SOP
标准包装: 100
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 8K (1K x 8)
速度: 400kHz,1MHz
接口: I²C,2 线串口
电源电压: 1.8 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOP
包装: 管件
其它名称: 1219-1011

24C04A, 24C08A, 24C16A
PIN DESCRIPTIONS
(A) SERIAL CLOCK (SCL)
The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of this clock is to
clock data out of the EEPROM device.
(B) DEVICE / CHIP SELECT ADDRESSES (A2, A1, A0)
These are the chip select input signals for the serial EEPROM devices. Typically, these signals are hardwired to
either V IH or V IL . If left unconnected, they are internally recognized as V IL . FT24C04A has A0 pin as no-connect.
FT24C08A has both A0 and A1 pins as no-connect. For FT24C16A, all device address pins (A0-A2) are no-
connect.
(C) SERIAL DATA LINE (SDA)
SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can be wired-
OR with other open-drain output devices.
(D) WRITE PROTECT (WP)
The FT24C04A/08A/16A devices have a WP pin to protect the whole EEPROM array from programming.
Programming operations are allowed if WP pin is left un-connected or input to V IL . Conversely all programming
functions are disabled if WP pin is connected to V IH or V CC . Read operations is not affected by the WP pin’s input
level.
Table A
Device
FT24C04A
FT24C08A
FT24C16A
Chip Select/Device
Address Pins Used
A2, A1
A2,
(None)
No-Connect Pins
A0
A1, A0
A2, A1, A0
Max number of similar
devices on the same bus
4
2
1
MEMORY ORGANIZATION
The FT24C04A/08A/16A devices have 32/64/128 pages respectively. Since each page has 16 bytes, random word
addressing to FT24C04A/08A/16A will require 9/10/11 bits data word addresses respectively.
DEVICE OPERATION
(A) SERIAL CLOCK AND DATA TRANSITIONS
The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when Serial clock
SCL is at V IL . Any SDA signal transition may interpret as either a START or STOP condition as described below.
(B) START CONDITION
With SCL ? V IH , a SDA transition from high to low is interpreted as a START condition. All valid commands
must begin with a START condition.
? 2009 Fremont Micro Devices Inc.
DS3001M-page 3
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