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参数资料
| 型号： | G2995P1UF |
| 厂商： | Global Mixed-mode Technology Inc. |
| 英文描述： | DDR Termination Regulator |
| 中文描述： | DDR终端稳压器 |
| 文件页数： | 10/12页 |
| 文件大小： | 272K |
| 代理商： | G2995P1UF |
Ver: 1.7
May 10, 2005
TEL: 886-3-5788833
http://www.gmt.com.tw
7
G2995
Global Mixed-mode Technology Inc.
Pin Description
NUMBER
NAME
FUNCTION
1
NC
2
GND
Ground
3
VSENSE
Feedback pin for regulating VTT
4
VREF
Buffered output that is a reference output of VDDQ/2
5
VDDQ
Input for internal reference which equals to VDDQ/2
6
AVIN
Analog input pin
7
PVIN
Power input pin
8
VTT
Output voltage for connection to termination resistors, equal to VDDQ/2
Block Diagram
Description
The G2995 is a linear bus termination regulator de-
signed to meet the JEDEC SSTL-2 and SSTL-3 (Se-
ries Stub Termination Logic) specifications for termina-
tion of DDR-SDRAM. The output, VTT, is capable of
sinking and sourcing current while regulating the out-
put voltage equal to VDDQ/2. The G2995 is designed
to maintain the excellent load regulation and with fast
response time to minimum the transition preventing
shoot-through. The G2995 also incorporates two dis-
tinct power rails that separates the analog circuitry
(AVIN) from the power output stage (PVIN). This
power rails split can be utilized to reduce the internal
power dissipation. And this also permits G2995 to pro-
vide a termination solution for the next generation of
DDR-SDRAM (DDR II).
Series Stub Termination Logic (SSTL) was created to
improve signal integrity of the data transmission
across the memory bus. This termination scheme is
essential to prevent data error from signal reflections
while transmitting at high frequencies encountered
with DDR-SDRAM. The most common form of termi-
nation is Class II single parallel termination. This in-
volves one RS series resistor from the chipset to the
memory and one RT termination resistor, both 25
Ω
typically. The resistors can be changed to scale the
current requirements from the G2995. This implemen-
tation can be seen below in Figure 1.
AVIN, PVIN
AVIN and PVIN are two independent input supply pins
for the G2995. AVIN is used to supply all the internal
analog circuits. PVIN is only used to supply the output
stage to create the regulated VTT. To keep the regula-
tion successfully, AVIN should be equal to or larger
than PVIN. Using a higher PVIN voltage will produce a
larger sourcing capability from VTT. But the internal
power loss will also increase and then the heat in-
creases. If the junction temperature exceeds the
thermal shutdown threshold than the G2995 will enter
the shutdown state, where VTT is tri-state and VREF re-
mains active.
For SSTL-2 applications, the AVIN and PVIN can be
short together at 2.5V to minimize the PCB complexity
and to reduce the bypassing capacitors for the two
supply pins separately.
V
DD
CHIPSET
R
S
V
TT
R
T
MENORY
V
REF
Figure 1. SSTL-Termination Scheme
V
DD
CHIPSET
R
S
V
TT
R
T
MENORY
V
REF
Figure 1. SSTL-Termination Scheme
+
-
+
-
PV
IN
AV
IN
V
DDQ
50k
GND
V
REF
V
SENSE
V
TT
+
-
+
-
+
-
+
-
PV
IN
AV
IN
V
DDQ
50k
GND
V
REF
V
SENSE
V
TT
相关PDF资料 |
PDF描述 |
|---|---|
| G2996F1UF | DDR I/II Termination Regulator |
| G2996F1U | DDR I/II Termination Regulator |
| G2996P1UF | DDR I/II Termination Regulator |
| G2996P1U | DDR I/II Termination Regulator |
| G5105TBU | Low-Noise Step-up DC-DC Converter |
相关代理商/技术参数 |
参数描述 |
|---|---|
| G2996 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DDR Termination Regulator with STR function.|Terminator Series |
| G2996F1U | 制造商:GMT 制造商全称:Global Mixed-mode Technology Inc 功能描述:DDR I/II Termination Regulator |
| G2996F1UF | 制造商:GMT 制造商全称:Global Mixed-mode Technology Inc 功能描述:DDR I/II Termination Regulator |
| G2996P1U | 制造商:GMT 制造商全称:Global Mixed-mode Technology Inc 功能描述:DDR I/II Termination Regulator |
| G2996P1UF | 制造商:GMT 制造商全称:Global Mixed-mode Technology Inc 功能描述:DDR I/II Termination Regulator |
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