参数资料
型号: GAL18V10B-20LP
厂商: Lattice Semiconductor Corporation
文件页数: 2/15页
文件大小: 0K
描述: IC GAL 10OUT MACROCELL 7.5NS 20
产品变化通告: Product Discontinuation 07/Sept/2010
标准包装: 1
可编程类型: EE PLD
宏单元数: 10
输入电压: 4.75 V ~ 5.25 V
速度: 20ns
安装类型: 通孔
封装/外壳: 20-DIP(0.300",7.62mm)
供应商设备封装: 20-PDIP
包装: 管件
其它名称: Q6330552
Specifications GAL18V10
9
fmax with Internal Feedback 1/(tsu+tcf)
Note: tcf is a calculated value, derived by sub-
tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-
natorial output is equal to tcf + tpd.
fmax with No Feedback
Note: fmax with no feedback may be less
than 1/(twh + twl). This is to allow for a
clock duty cycle of other than 50%.
Note: fmax with external feedback is cal-
culated from measured tsu and tco.
fmax with External Feedback 1/(tsu+tco)
REGISTER
LOGIC
ARRAY
CLK
tsu + th
TEST POINT
C *
L
FROM OUTPUT (O/Q)
UNDER TEST
+5V
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
R2
R1
REGISTER
LOGIC
ARRAY
tco
tsu
CLK
Output Load Conditions (see figure)
Test Condition
R1
R2
CL
A
300Ω
390Ω
50pF
B
Active High
390Ω
50pF
Active Low
300Ω
390Ω
50pF
C
Active High
390Ω
5pF
Active Low
300Ω
390Ω
5pF
Input Pulse Levels
GND to 3.0V
Input Rise and
-7/-10
2ns 10% – 90%
Fall Times
-15/-20
3ns 10% – 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
See Figure
3-state levels are measured 0.5V from steady-state active
level.
CLK
REGISTER
LOGIC
ARRAY
tcf
tpd
fmax Descriptions
Switching Test Conditions
ALL
DEVICES
DISCONTINUED
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