参数资料
型号: GL602USB-A
厂商: Electronic Theatre Controls, Inc.
英文描述: USB KEYBOARD MICROCONTROLLER
中文描述: USB键盘单片机
文件页数: 3/35页
文件大小: 201K
代理商: GL602USB-A
Revision 1.6
-11-
02/28/2000
4.2 USB FUNCTION REGISTERS
Table 4-1 USB Function Register Summary
Address
Name
Function
10h
DEVCTL
Device control register
11h
EVTFLG
Event flag register
12h
DEVADR
USB device address register
13h
RXCTL0
Endpoint 0 receive control register
14h
TXCTL0
Endpoint 0 transmit control register
15h
TXCTL123
Endpoint 1/2/3 transmit control register
16h
FFDAT0
Endpoint 0 FIFO data port
17h
FFDAT123
Endpoint 1/2/3 FIFO data port
18h
DRVSEL
Key matrix drive pin control register
19h
SENSE
Key matrix sense register
1Ah
FFRST
FIFO reset register
1Bh
MODESEL
USB mode select register
1Ch
Reserved
1Dh
EPSEL
Endpoint select register
1Eh
SERCTL
PS/2 mouse port control register
1Fh
SERDAT
PS/2 mouse port data register
DEVCTL (Address 10h, Device control register)
R/W
[1]
R/W
EP3STL
EP2STL
EP1STL
EP0STL
WAKE
WKDIS
PWRDN
EP3STL: Endpoint 3 stall bit
1: Endpoint 3 will respond with a STALL to a valid transaction
0: Endpoint 3 will not respond with a STALL to a valid transaction
EP2STL: Endpoint 2 stall bit
1: Endpoint 2 will respond with a STALL to a valid transaction
0: Endpoint 2 will not respond with a STALL to a valid transaction
EP1STL: Endpoint 1 stall bit
1: Endpoint 1 will respond with a STALL to a valid transaction
0: Endpoint 1 will not respond with a STALL to a valid transaction
EP0STL: Endpoint 0 stall bit
1: Endpoint 0 will respond with a STALL to a valid transaction.
0: Endpoint 0 will not respond with a STALL to a valid transaction
WAKE: Wake-up bit
1: Set this bit to wake up host controller by placing USB bus into K state
0: Clear this bit to force USB bus leave K state
WKDIS: Wake-up disable bit
1: Disable remote wake-up capability
0: Enable remote wake-up capability
PWRDN: Power-down mode bit
1: Entering power-down mode
If USB suspend is detected, firmware should set this bit to enter power-down mode. In power-down mode,
6MHz crystal clock will be stopped. Hardware will automatically clear PWRDN bit upon hardware reset,
USB D+/D- toggle, SENSE1~SENSE8 at logic ‘0’, or Port 1.1 at logic ‘0’.
Value on POR: “0 0 0 0 0 0 0 0”
Note 1: “R/W” means readable and writable bit
EVTFLG (Address 11h, Event flag register)
R/W1C
[1]
R/W1C
WAKEUP
RESUME
SUSPD
EP3TX
EP2TX
EP1TX
EP0TX
EP0RX
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