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参数资料
| 型号： | GLT5160L16-10FJ |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM |
| 中文描述： | 1,600（2 -银行甲524288字× 16位）同步DRAM |
| 文件页数： | 2/45页 |
| 文件大小： | 399K |
| 代理商： | GLT5160L16-10FJ |
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2
G-LINK Technology
DEC. 2003 (Rev. 2.4)
F
UNCTIONAL
B
LOCK
D
IAGRAM
A[10:0]
DQ[15:0]
Figure 1. 16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM
C
Address Buffer
BA
CLK
CKE
CS
RAS
CAS
WE
Clock Buffer
Control
Signal Buffer
DQML
DQMU
Mode
Register
Memory Array
Bank #0
Memory Array
Bank #1
I/O Buffer
Signal Description
Signal
Type
Description
CLK
Input
Master Clock: All other inputs are referenced to the rising edge of CLK.
CKE
Input
Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased.
CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous
input. Self refresh is maintained as long as CKE is low.
CS
Input
Chip Select: When CS is high, any command means No Operation.
RAS, CAS, WE
Input
Combination of RAS, CAS, WE defines basic commands.
A[10:0]
Input
A[10:0] specify the Row / Column Address in conjunction with BA. The Row Address is specified by A[10:0].
The Column Address is specified by A[7:0]. A[10] is also used to indicate precharge option. When A[10] is
high at a read / write command, an auto precharge is performed. When A[10] is high at a precharge command,
both banks are precharged.
BA
Input
Bank Address: BA is not simply A[11]. BA specifies the bank to which a command is applied. BA must be set
with ACT, PRE, READ, WRITE commands.
DQ[15:0]
Input / Output
Data In and Data out are referenced to the rising edge of CLK.
DQML
Input
Lower Din[7:0] Mask / Lower Output[7:0] Disable: When DQML is high in burst write, lower Din[7:0] for the
current cycle is masked. When DQML is high in burst read, lower Dout[7:0] is disabled at the next but one
cycle.
DQMU
Input
Upper Din[15:8] Mask / Upper Output[15:8] Disable: When DQMU is high in burst write, upper Din(8-15) for
the current cycle is masked. When DQMU is high in burst read, upper Dout[15:8] is disabled at the next but
one cycle.
V
DD
, V
SS
V
DDQ
, V
SSQ
Power Supply
Power Supply for the memory array and peripheral circuitry.
Power Supply
V
DDQ
and V
SSQ
are supplied to the Output Buffers only.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| GLT5160L16-10TC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM |
| GLT5160L16-6FJ | 制造商:未知厂家 制造商全称:未知厂家 功能描述:16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM |
| GLT5160L16-6TC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM |
| GLT5160L16-7FJ | 制造商:未知厂家 制造商全称:未知厂家 功能描述:16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM |
| GLT5160L16-7TC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM |
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