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参数资料
| 型号： | GS78108AGB-12IT |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | SRAM |
| 英文描述： | 1M X 8 STANDARD SRAM, 12 ns, PBGA119 |
| 封装： | 14 X 22 MM, 1.27 MM PITCH, ROHS COMPLIANT, FPBGA-119 |
| 文件页数： | 8/12页 |
| 文件大小： | 351K |
| 代理商： | GS78108AGB-12IT |
DQ
VT = 1.4 V
50
Ω
30pF1
DQ
3.3 V
Output Load 1
Output Load 2
589
Ω
434
Ω
5pF1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted
3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ.
Parameter
Conditions
Input high level
VIH = 2.4 V
Input low level
VIL = 0.4 V
Input rise time
tr = 1 V/ns
Input fall time
tf = 1 V/ns
Input reference level
1.4 V
Output reference level
1.4 V
Output load
Fig. 1& 2
GS78108AB
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2007
5/12
2003, GSI Technology
AC Test Conditions
AC Characteristics
Read Cycle
Parameter
Symbol
-8
-10
-12
Unit
Min
Max
Min
Max
Min
Max
Read cycle time
tRC
8
—
10
—
12
—
ns
Address access time
tAA
—
8
—
10
—
12
ns
Chip enable access time (CE)
tAC
—
8
—
10
—
12
ns
Output enable to output valid (OE)
tOE
—
3.5
—
4
—
5
ns
Output hold from address change
tOH
3
—
3
—
3
—
ns
Chip enable to output in low Z (CE)
t *
3
—
3
—
3
—
ns
Output enable to output in low Z (OE)
t *
0
—
0
—
0
—
ns
Chip disable to output in High Z (CE)
t *
—
4
—
5
—
6
ns
Output disable to output in High Z (OE)
t
*
—
3.5
—
4
—
5
ns
LZ
OLZ
HZ
OHZ
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| GS78108AGB-15I | 制造商:GSI 制造商全称:GSI Technology 功能描述:1M x 8 8Mb Asynchronous SRAM |
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