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参数资料
| 型号： | GS81302T10E-350I |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | SRAM |
| 英文描述： | 16M X 9 DDR SRAM, 0.45 ns, PBGA165 |
| 封装： | 15 X 17 MM, 1 MM PITCH, FPBGA-165 |
| 文件页数： | 1/31页 |
| 文件大小： | 1202K |
| 代理商： | GS81302T10E-350I |
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GS81302T07/10/19/37E-450/400/350/333/300
144Mb SigmaDDRTM-II+
Burst of 2 SRAM
450 MHz–300 MHz
1.8 V VDD
1.8 V or 1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.03 4/2011
1/31
2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
2.0 Clock Latency
Simultaneous Read and Write SigmaDDR Interface
Common I/O bus
JEDEC-standard pinout and package
Double Data Rate interface
Byte Write controls sampled at data-in time
Burst of 2 Read and Write
On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) inputs
1.8 V +100/–100 mV core power supply
1.5 V or 1.8 V HSTL Interface
Pipelined read operation with self-timed Late Write
Fully coherent read and write pipelines
ZQ pin for programmable output drive strength
Data Valid pin (QVLD) Support
IEEE 1149.1 JTAG-compliant Boundary Scan
165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
RoHS-compliant 165-bump BGA package available
SigmaDDR Family Overview
The GS81302T07/10/19/37E are built in compliance with the
SigmaDDR-II+ SRAM pinout standard for Common I/O
synchronous SRAMs. They are 150,994,944-bit (144Mb)
SRAMs. The GS81302T07/10/19/37E SigmaDDR-II+
SRAMs are just one element in a family of low power, low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
Clocking and Addressing Schemes
The GS81302T07/10/19/37E SigmaDDR-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Because Common I/O SigmaDDR-II+ RAMs always transfer
data in two packets, A0 is internally set to 0 for the first read
or write transfer, and automatically incremented by 1 for the
next transfer. Because the LSB is tied off internally, the
address field of a SigmaDDR-II+ B2 RAM is always one
address pin less than the advertised index depth (e.g., the 8M x
18 has a 4M addressable index).
Parameter Synopsis
-450
-400
-350
-333
-300
tKHKH
2.2 ns
2.5 ns
2.86 ns
3.0 ns
3.3 ns
tKHQV
0.45 ns
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
Bottom View
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相关代理商/技术参数 |
参数描述 |
|---|---|
| GS81302T36GE-333 | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V 144MBIT 4MX36 0.45NS 165FPBGA - Trays |
| GS81302T36GE-333I | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V 144MBIT 4MX36 0.45NS 165FPBGA - Trays |
| GS815018AB | 制造商:GSI 制造商全称:GSI Technology 功能描述:1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM |
| GS815018AB-250 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V 18MBIT 1MX18 2NS 119FPBGA - Trays |
| GS815018AB-250I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V 18MBIT 1MX18 2NS 119FPBGA - Trays |
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