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参数资料
| 型号： | GS815032 |
| 厂商： | GSI TECHNOLOGY |
| 英文描述： | 16Mb（512K x 32Bit）Synchronous Burst SRAM(16M位（512K x 32位）同步静态RAM（带2位脉冲地址计数器）) |
| 中文描述： | 16Mb的（为512k × 32位）同步突发静态存储器（1,600位（512k × 32的位）同步静态随机存储器（带2位脉冲地址计数器）） |
| 文件页数： | 1/26页 |
| 文件大小： | 516K |
| 代理商： | GS815032 |
Rev: 1.02 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/26
2000, Giga Semiconductor, Inc.
Preliminary
GS815018/32/36T-225/200/180/166/150/133
1M x 18, 512K x 32, 512K x 36
16Mb Sync Burst SRAMs
225 MHz–133 MHz
3.3 V V
DD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
FT pin for user-configurable flow through or pipelined
operation
Single Cycle Deselect (SCD) operation
3.3 V +10%/–5% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 100-lead TQFP package
-225 -200 -180 -166 -150 -133 Unit
Pipeline
3-1-1-1
tCycle
Curr (x18)
Curr (x32)
Curr (x36)
410
370
Flow
Through
2-1-1-1
Curr (x18)
Curr (x32)
Curr (x36)
240
210
Functional Description
Applications
The GS815018/32/36T is a 18,874,368-bit (16,777,216-bit for
x32 version) high performance synchronous SRAM with a 2-
bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output Register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
SCD Pipelined Reads
The GS815018/32/36T is a SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS815018/32/36T operates on a 3.3 V power supply. All
input are 3.3 V- and 2.5 V-compatible. Separate output power
(V
DDQ
) pins are used to decouple output noise from the
internal circuits and are 3.3 V- and 2.5 V-compatible.
t
KQ
2.5
4.4
350
410
3.0
5.0
315
370
3.2
5.5
290
340
340
8
10
185
210
210
3.5
6.0
270
315
315
8.5
10
185
210
210
3.8
6.6
250
290
290
10
10
185
210
210
4.0
7.5
230
260
260
11
15
140
160
160
ns
ns
mA
mA
mA
ns
ns
mA
mA
mA
t
KQ
tCycle
7.0
8.5
205
240
7.5
10
185
210
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