参数资料
型号: GS8150F32
厂商: GSI TECHNOLOGY
英文描述: 16Mb(512K x 32Bit)Synchronous Burst SRAM(16M位(512K x 32位)同步静态RAM(带2位脉冲地址计数器))
中文描述: 16Mb的(为512k × 32位)同步突发静态存储器(1,600位(512k × 32的位)同步静态随机存储器(带2位脉冲地址计数器))
文件页数: 7/23页
文件大小: 456K
代理商: GS8150F32
Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
7/23
2000, Giga Semiconductor, Inc.
Preliminary
GS8150F18/32/36T-7/8/8.5/10/11
Mode Pin Functions
Note:
There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as
specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
BPR 1999.05.18
Byte Write Truth Table
Notes:
1.
2.
3.
4.
All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
Byte Write Enable inputs B
A
, B
B
, B
C
, and/or B
D
may be used in any combination with BW to write single or multiple bytes.
All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
Bytes “
C
” and “
D
” are only available on the x32 and x36 versions.
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
H
Linear Burst
Interleaved Burst
Active
Standby, I
DD
= I
SB
Power Down Control
ZZ
L or NC
H
Function
GW
BW
B
A
B
B
B
C
B
D
Notes
Read
H
H
X
X
X
X
1
Read
H
L
H
H
H
H
1
Write byte a
H
L
L
H
H
H
2, 3
Write byte b
H
L
H
L
H
H
2, 3
Write byte c
H
L
H
H
L
H
2, 3, 4
Write byte d
H
L
H
H
H
L
2, 3, 4
Write all bytes
H
L
L
L
L
L
2, 3, 4
Write all bytes
L
X
X
X
X
X
Note: The burst counter wraps to initial state on the 5th clock.
I
nterleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
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