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参数资料
| 型号： | GS8151Z18 |
| 厂商： | GSI TECHNOLOGY |
| 英文描述： | 16Mb Pipelined and Flow Through Synchronous NBT SRAM(16M位流水线式和流通型同步NBT静态RAM) |
| 中文描述： | 16Mb的流水线和流量，通过同步唑的SRAM（1,600位流水线式和流通型同步唑静态内存） |
| 文件页数： | 12/27页 |
| 文件大小： | 683K |
| 代理商： | GS8151Z18 |
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Rev: 1.01 1/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
12/27
2000, Giga Semiconductor, Inc.
Preliminary
GS8151Z18/36T-225/200/180/166/150/133
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Mode Pin Functions
Note:
There are pull up devices on the LBO, DP, and FT pins and a pull down device on the ZZ pin, so those input pins can be
unconnected and the chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
BPR 1999.05.18
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Active
Standby, I
DD
= I
SB
Check for Odd Parity
Check for Even Parity
H or NC
L
H or NC
L or NC
Output Register Control
FT
Power Down Control
ZZ
H
ByteSafe Data Parity Control
DP
L
H or NC
Note: The burst counter wraps to initial state on the 5th clock.
I
nterleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0]
A[1:0]
A[1:0]
A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
A[1:0]
A[1:0]
A[1:0]
A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
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相关代理商/技术参数 |
参数描述 |
|---|---|
| GS815V018AB-250 | 制造商:GSI Technology 功能描述:GS815V018AB-250 - Trays |
| GS815V018AB-250I | 制造商:GSI Technology 功能描述:GS815V018AB-250I - Trays |
| GS815V018AB-300 | 制造商:GSI Technology 功能描述:GS815V018AB-300 - Trays |
| GS815V018AB-300I | 制造商:GSI Technology 功能描述:GS815V018AB-300I - Trays |
| GS815V018AB-333 | 制造商:GSI Technology 功能描述:GS815V018AB-333 - Trays |
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