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参数资料
| 型号： | GS8151Z18 |
| 厂商： | GSI TECHNOLOGY |
| 英文描述： | 16Mb Pipelined and Flow Through Synchronous NBT SRAM(16M位流水线式和流通型同步NBT静态RAM) |
| 中文描述： | 16Mb的流水线和流量，通过同步唑的SRAM（1,600位流水线式和流通型同步唑静态内存） |
| 文件页数： | 13/27页 |
| 文件大小： | 683K |
| 代理商： | GS8151Z18 |
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Rev: 1.01 1/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
13/27
2000, Giga Semiconductor, Inc.
Preliminary
GS8151Z18/36T-225/200/180/166/150/133
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I
SB
2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I
SB
2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipelinemode via the FT signal found
on Pin 14. Not all vendors offer this option, however most mark Pin 14 as V
DD
or V
DDQ
on pipelined parts and V
SS
on flow
through parts. GSI NBT SRAMs are fully compatible with these sockets.
Pin 66, a No Connect (NC) on GSI’s GS8160Z18/36 NBT SRAM, the Parity Error open drain output on GSI’s GS8161Z18/36
NBT SRAM, is often marked as a power pin on other vendor’s NBT compatible SRAMs. Specifically, it is marked V
DD
or V
DDQ
on pipelined parts and V
SS
on flow through parts. Users of GSI NBT devices who are not actually using the ByteSafe parity
feature may want to design the board site for the RAM with Pin 66 tied high through a 1k ohm resistor in Pipeline mode
applications or tied low in Flow Through mode applications in order to keep the option to use non-configurable devices open. By
using the pull-up resistor, rather than tying the pin to one of the power rails, users interested in upgrading to GSI’s ByteSafe NBT
SRAMs (GS8161Z18/36), featuring Parity Error detection and JTAG Boundary Scan, will be ready for connection to the active
low, open drain Parity Error output driver at pin 66 on GSI’s TQFP ByteSafe RAMs.
ByteSafe
Parity Functions
In x32/x16 mode this RAM features a parity encoding and checking function. It is assumed that the RAM is being used in x32/x16
mode because there is no source for parity bits from the system. So, in x32/x16 mode, the device generates parity and stores it
along with written data. It is also assumed that there is no facility for parity checking, so the RAM checks read parity and reports an
error in the cycle following parity check. In x32/x16 mode the device does not drive the 9th data output, even though the internal
ByteSafe parity encoding has been activated. A ByteSafe SRAM, used in x32/x16 mode, allows parity protection of data in
applications where parity encoding or checking are not otherwise available. As in any system that checks read parity, reads of un-
written memory locations may well produce parity errors. Initialization of the memory should be implemented to avoid this issue.
This SRAM includes a write data parity check that checks the validity of data coming into the RAM on write cycles. In Flow
Through mode, write data errors are reported in the cycle following the data input cycle. In Pipeline mode, write data errors are
reported one clock cycle later. (See timing diagram below.) The Data Parity Mode (DP) pin must be tied high to set the RAM to
CK
ZZ
tZZR
tZZH
tZZS
~
~
Sleep
相关PDF资料 |
PDF描述 |
|---|---|
| GS8151Z36 | 16Mb Pipelined and Flow Through Synchronous NBT SRAM(16M位流水线式和流通型同步NBT静态RAM) |
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| GS8152Z18 | 16Mb Pipelined and Flow Through Synchronous NBT SRAM(16M位流水线式和流通型同步NBT静态RAM) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| GS815V018AB-250 | 制造商:GSI Technology 功能描述:GS815V018AB-250 - Trays |
| GS815V018AB-250I | 制造商:GSI Technology 功能描述:GS815V018AB-250I - Trays |
| GS815V018AB-300 | 制造商:GSI Technology 功能描述:GS815V018AB-300 - Trays |
| GS815V018AB-300I | 制造商:GSI Technology 功能描述:GS815V018AB-300I - Trays |
| GS815V018AB-333 | 制造商:GSI Technology 功能描述:GS815V018AB-333 - Trays |
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