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参数资料
| 型号： | GS8161V36CGD-333I |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | DRAM |
| 英文描述： | 1M x 18 and 512K x 36 18Mb Sync Burst SRAMs |
| 中文描述： | 512K X 36 CACHE SRAM, 4.5 ns, PBGA165 |
| 封装： | 13 X 15 MM, 1 MM PITCH, LEAD FREE, FBGA-165 |
| 文件页数： | 15/28页 |
| 文件大小： | 584K |
| 代理商： | GS8161V36CGD-333I |
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GS8161V18/36CD-333/300/250
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 2/2005
15/28
2004, GSI Technology
Notes:
1.
2.
These parameters are sampled and are not 100% tested
ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
AC Electrical Characteristics
Parameter
Symbol
-333
-300
-250
Unit
Min
Max
Min
Max
Min
Max
Pipeline
Clock Cycle Time
tKC
3.0
—
3.3
—
4.0
—
ns
Clock to Output Valid
tKQ
—
2.5
—
2.5
—
2.5
ns
Clock to Output Invalid
tKQX
1.5
—
1.5
—
1.5
—
ns
Clock to Output in Low-Z
tLZ
1
1.5
—
1.5
—
1.5
—
ns
Setup time
tS
1.0
—
1.0
—
1.2
—
ns
Hold time
tH
0.1
—
0.1
—
0.2
—
ns
Flow Through
Clock Cycle Time
tKC
4.5
—
5.0
—
5.5
—
ns
Clock to Output Valid
tKQ
—
4.5
—
5.0
—
5.5
ns
Clock to Output Invalid
tKQX
2.0
—
2.0
—
2.0
—
ns
Clock to Output in Low-Z
tLZ
1
2.0
—
2.0
—
2.0
—
ns
Setup time
tS
1.3
—
1.4
—
1.5
—
ns
Hold time
tH
0.3
—
0.4
—
0.5
—
ns
Clock HIGH Time
tKH
1.0
—
1.0
—
1.3
—
ns
Clock LOW Time
tKL
1.2
—
1.2
—
1.5
—
ns
Clock to Output in
High-Z
tHZ
1
1.5
2.5
1.5
2.5
1.5
2.5
ns
G to Output Valid
tOE
—
2.5
—
2.5
—
2.5
ns
G to output in Low-Z
tOLZ
1
0
—
0
—
0
—
ns
G to output in High-Z
tOHZ
1
—
2.5
—
2.5
—
2.5
ns
ZZ setup time
tZZS
2
5
—
5
—
5
—
ns
ZZ hold time
tZZH
2
1
—
1
—
1
—
ns
ZZ recovery
tZZR
20
—
20
—
20
—
ns
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