- 您现在的位置：买卖IC网 > PDF目录383032 > GS816272 (GSI TECHNOLOGY) 16Mb（256K x 72Bit）S/DCD Sync Burst SRAM(16M位（256K x 72位）可选单/双循环取消同步静态RAM(带2位脉冲地址计数器)) PDF资料下载
参数资料
| 型号： | GS816272 |
| 厂商： | GSI TECHNOLOGY |
| 英文描述： | 16Mb（256K x 72Bit）S/DCD Sync Burst SRAM(16M位（256K x 72位）可选单/双循环取消同步静态RAM(带2位脉冲地址计数器)) |
| 中文描述： | 16Mb的（256 × 72Bit）的S /双氰胺同步突发静态存储器（1,600位（256 × 72位）可选单/双循环取消同步静态随机存储器（带2位脉冲地址计数器）） |
| 文件页数： | 1/38页 |
| 文件大小： | 826K |
| 代理商： | GS816272 |
当前第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页
Rev: 2.10 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
1/38
1999, Giga Semiconductor, Inc.
Preliminary
GS816218/36/72B-225/200/180/166/150/133
1M x 18, 512K x 36, 256K x 72
16Mb S/DCD Sync Burst SRAMs
225 MHz
–
133MHz
2.5 V V
DD
2.5 V or 3.3 V I/O
119- and 209-Pin BGA
Commercial Temp
Industrial Temp
Features
FT pin for user-configurable flow through or pipeline operation
Single/Dual Cycle Deselect selectable
IEEE 1149.1 JTAG-compatible Boundary Scan
On-chip read parity checking; even or odd selectable
ZQ mode pin for user-selectable high/low output drive
On-chip parity encoding and error detection
2.5 V +10%/–5% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to SCD x18/x36 Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 119- and 209-bump BGA package
Functional Description
Applications
The GS816218/36/72B is a 18,874,368-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
SCD and DCD Pipelined Reads
The GS816218/36/72B is a SCD (Single Cycle Deselect) and
DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
ByteSafe Parity Functions
The GS816218/36/72B features ByteSafe data security functions.
See the detailed discussion following.
FLXDrive
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS816218/36/72B operates on a 2.5 V power supply. All
input are 3.3 V- and 2.5 V-compatible. Separate output power
(V
DDQ
) pins are used to decouple output noise from the internal
circuits and are 3.3 V- and 2.5 V-compatible.
-225 -200 -180 -166 -150 -133 Unit
7.0
8.5
205
240
325
285
285
285
Flow
Through
2-1-1-1
t
KQ
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
7.5
10.0
185
210
8.0
10.0
185
210
8.5
10.0
185
210
10.0
10.0
185
210
285
11.0
15.0
140
160
205
ns
ns
mA
mA
mA
相关PDF资料 |
PDF描述 |
|---|---|
| GS8162Z18BGB-200I | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8162Z18BB | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8162Z18BB-150 | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8162Z18BB-150I | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8162Z18BB-200 | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| GS816272C200 | 制造商:GSI 功能描述:New |
| GS816272CC-150 | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 18MBIT 256KX72 7.5NS/3.8NS 209FBGA - Trays |
| GS816272CC-150I | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 18MBIT 256KX72 7.5NS/3.8NS 209FBGA - Trays |
| GS816272CC-150IV | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V/2.5V 18MBIT 256KX72 7.5NS/3.8NS 209FBGA - Trays |
| GS816272CC-150V | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V/2.5V 18MBIT 256KX72 7.5NS/3.8NS 209FBGA - Trays |
发布紧急采购，3分钟左右您将得到回复。