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参数资料
| 型号： | GS816272 |
| 厂商： | GSI TECHNOLOGY |
| 英文描述： | 16Mb（256K x 72Bit）S/DCD Sync Burst SRAM(16M位（256K x 72位）可选单/双循环取消同步静态RAM(带2位脉冲地址计数器)) |
| 中文描述： | 16Mb的（256 × 72Bit）的S /双氰胺同步突发静态存储器（1,600位（256 × 72位）可选单/双循环取消同步静态随机存储器（带2位脉冲地址计数器）） |
| 文件页数： | 9/38页 |
| 文件大小： | 826K |
| 代理商： | GS816272 |
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Rev: 2.10 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
9/38
1999, Giga Semiconductor, Inc.
Preliminary
GS816218/36/72B-225/200/180/166/150/133
Mode Pin Functions
Note:
There are pull-up devices on the ZQ, SCD DP, and FT pins and pull-down devices on the PE and ZZ pins, so those input pins can
be unconnected and the chip will operate in the default states as specified in the above tables.
Enable / Disable Parity I/O Pins
This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16,
x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE
deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits
generated and read into the ByteSafe parity circuits.
Burst Counter Sequences
Linear Burst Sequence
BPR 1999.05.18
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
H
L
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Active
Standby, I
DD
= I
SB
Dual Cycle Deselect
Single Cycle Deselect
Check for Odd Parity
Check for Even Parity
Activate 9th I/O’s (x18/36 Mode)
Deactivate 9th I/O’s (x16/32 Mode)
High Drive (Low Impedance)
Low Drive (High Impedance)
Output Register Control
FT
H or NC
L or NC
Power Down Control
ZZ
H
Single / Dual Cycle Deselect Control
SCD
L
H or NC
L
H or NC
L or NC
H
L
H or NC
ByteSafe Data Parity Control
DP
Parity Enable
PE
FLXDrive Output Impedance Control
ZQ
Note: The burst counter wraps to initial state on the 5th clock.
I
nterleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
相关PDF资料 |
PDF描述 |
|---|---|
| GS8162Z18BGB-200I | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8162Z18BB | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8162Z18BB-150 | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8162Z18BB-150I | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8162Z18BB-200 | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| GS816272C200 | 制造商:GSI 功能描述:New |
| GS816272CC-150 | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 18MBIT 256KX72 7.5NS/3.8NS 209FBGA - Trays |
| GS816272CC-150I | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 18MBIT 256KX72 7.5NS/3.8NS 209FBGA - Trays |
| GS816272CC-150IV | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V/2.5V 18MBIT 256KX72 7.5NS/3.8NS 209FBGA - Trays |
| GS816272CC-150V | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V/2.5V 18MBIT 256KX72 7.5NS/3.8NS 209FBGA - Trays |
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