参数资料
型号: GS84018AB-190
厂商: GSI TECHNOLOGY
元件分类: SRAM
英文描述: 256K X 18 CACHE SRAM, 7.5 ns, PBGA119
封装: FPBGA-119
文件页数: 3/31页
文件大小: 1248K
代理商: GS84018AB-190
Mode Pin Functions
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H or NC
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
GS84018/32/36AT/B-190/180/166/150/100
Rev: 1.18 3/2007
11/31
1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Note:
There are pull-up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above tables.
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Burst Counter Sequences
相关PDF资料
PDF描述
GS840E18AGT-150T 256K X 18 CACHE SRAM, 10 ns, PQFP100
GS840E18AT-166IT 256K X 18 CACHE SRAM, 8.5 ns, PQFP100
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GS840H18AT-100T 256K X 18 CACHE SRAM, 12 ns, PQFP100
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