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参数资料
| 型号： | GS8642ZV18GE-167 |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | SRAM |
| 英文描述： | 4M X 18 ZBT SRAM, 8 ns, PBGA165 |
| 封装： | 17 X 15 MM, 1 MM PITCH, FBGA-165 |
| 文件页数： | 1/37页 |
| 文件大小： | 1118K |
| 代理商： | GS8642ZV18GE-167 |
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Product Preview
GS8642ZV18(B/E)/GS8642ZV36(B/E)/GS8642ZV72(C)
72Mb Pipelined and Flow Through
Synchronous NBT SRAM
300 MHz–167 MHz
1.8 V VDD
1.8 V I/O
119-, 165-, & 209-Pin BGA
Commercial Temp
Industrial Temp
Rev: 1.00 9/2004
1/37
2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM, NoBL and
ZBT SRAMs
1.8 V +10%/–10% core power supply
1.8 V I/O supply
User-configurable Pipeline and Flow Through mode
ZQ mode pin for user-selectable high/low output drive
IEEE 1149.1 JTAG-compatible Boundary Scan
LBO pin for Linear or Interleave Burst mode
Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ Pin for automatic power-down
JEDEC-standard 119-, 165- or 209-Bump BGA package
Functional Description
The GS8642ZV18/36/72 is a 72Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8642ZV18/36/72 may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8642ZV18/36/72 is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump, 165-bump or 209-bump BGA package.
Parameter Synopsis
-300
-250
-200
-167
Unit
Pipeline
3-1-1-1
tKQ(x18/x36)
tKQ(x72)
tCycle
2.3
3.0
3.3
2.5
3.0
4.0
3.0
5.0
3.5
6.0
ns
Curr (x18)
Curr (x36)
Curr (x72)
400
480
590
340
410
520
290
350
435
260
305
380
mA
Flow Through
2-1-1-1
tKQ
tCycle
5.5
6.5
7.5
8.0
ns
Curr (x18)
Curr (x36)
Curr (x72)
285
330
425
245
280
370
220
250
315
210
240
300
mA
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PDF描述 |
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| GS88218BD-200V | 512K X 18 CACHE SRAM, 6.5 ns, PBGA165 |
| GLCB36D-4Q04 | SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 0.5A, 120VDC, PANEL MOUNT-THREADED |
| GSCC01A1B-1Q02 | SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 0.55A, 125VDC, 53.5mm, PANEL MOUNT |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| GS8642ZV36B-167 | 制造商:GSI 制造商全称:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8642ZV36B-167I | 制造商:GSI 制造商全称:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8642ZV36B-200 | 制造商:GSI 制造商全称:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8642ZV36B-200I | 制造商:GSI 制造商全称:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8642ZV36B-250 | 制造商:GSI 制造商全称:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
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