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参数资料
| 型号： | GS8662T06BD-350T |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | SRAM |
| 英文描述： | 8M X 8 DDR SRAM, 0.45 ns, PBGA165 |
| 封装： | 13 X 15 MM, 1 MM PITCH, FPBGA-165 |
| 文件页数： | 1/33页 |
| 文件大小： | 651K |
| 代理商： | GS8662T06BD-350T |
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72Mb SigmaDDRTM-II+
Burst of 2 SRAM
550 MHz–350 MHz
1.8 V VDD
1.8 V or 1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.02 3/2011
1/33
2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T20/38BD-550/500/450/400/350
GS8662T06/11BD-500/450/400/350
Features
2.5 Clock Latency
Simultaneous Read and Write SigmaDDRTM Interface
JEDEC-standard pinout and package
Double Data Rate interface
Byte Write controls sampled at data-in time
Burst of 2 Read and Write
On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) inputs
1.8 V +100/–100 mV core power supply
1.5 V or 1.8 V HSTL Interface
Pipelined read operation
Fully coherent read and write pipelines
ZQ pin for programmable output drive strength
Data Valid Pin (QVLD) Support
IEEE 1149.1 JTAG-compliant Boundary Scan
165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
RoHS-compliant 165-bump BGA package available
SigmaDDR-II Family Overview
The GS8662T06/11/20/38BD are built in compliance with the
SigmaDDR-II+ SRAM pinout standard for Common I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
SRAMs. The GS8662T06/11/20/38BD SigmaDDR-II+
SRAMs are just one element in a family of low power, low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
Clocking and Addressing Schemes
The GS8662T06/11/20/38BD SigmaDDR-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Because Common I/O SigmaDDR-II+ RAMs always transfer
data in two packets, A0 is internally set to 0 for the first read
or write transfer, and automatically incremented by 1 for the
next transfer. Because the LSB is tied off internally, the
address field of a SigmaDDR-II+ B2 RAM is always one
address pin less than the advertised index depth (e.g., the 4M x
18 has a 2M addressable index).
Parameter Synopsis (x18/x36)
-550
-500
-450
-400
-350
tKHKH
1.81 ns
2.0 ns
2.2 ns
2.5 ns
2.86 ns
tKHQV
0.29ns
0.33 ns
0.37 ns
0.45 ns
Parameter Synopsis (x8/x9)
-500
-450
-400
-350
tKHKH
2.0 ns
2.2 ns
2.5 ns
2.86 ns
tKHQV
0.33 ns
0.37ns
0.45 ns
相关PDF资料 |
PDF描述 |
|---|---|
| GS8672Q38BE-500I | 2M X 36 QDR SRAM, 0.45 ns, PBGA165 |
| GS880F32AGT-5.5IT | 256K X 32 CACHE SRAM, 5.5 ns, PQFP100 |
| GS880F32BGT-7IT | 256K X 32 CACHE SRAM, 7 ns, PQFP100 |
| GSAA07C-Q01 | SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 0.1A, 50VDC, PANEL MOUNT |
| GSAC36C-6Q02 | SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 0.1A, 50VDC, PANEL MOUNT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| GS8662T06BD-450 | 制造商:GSI Technology 功能描述:GS8662T06BD-450 - Trays |
| GS8662T06BD-500 | 制造商:GSI Technology 功能描述:GS8662T06BD-500 - Trays |
| GS8662T06BD-550 | 制造商:GSI Technology 功能描述:GS8662T06BD-550 - Trays |
| GS8662T07BD-450 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8662T08BD-400 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
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