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参数资料
| 型号： | GS880V18BT-250T |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | SRAM |
| 英文描述： | 512K X 18 CACHE SRAM, 5.5 ns, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 1/23页 |
| 文件大小： | 600K |
| 代理商： | GS880V18BT-250T |
GS880V18/32/36BT-333/300/250/200
512K x 18, 256K x 32, 256K x 36
9Mb Sync Burst SRAMs
333 MHz–200 MHz
1.8 V VDD
1.8 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Rev: 1.02 3/2005
1/23
2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
FT pin for user-configurable flow through or pipeline
operation
Single Cycle Deselect (SCD) operation
1.8 V +10%/–10% core power supply
1.8 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 100-lead TQFP package
Pb-Free 100-lead TQFP package available
Functional Description
Applications
The GS880V18/32/36BT is a 9,437,184-bit (8,388,608-bit for
x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
SCD Pipelined Reads
The GS880V18/32/36BT is a SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS880V18/32/36BT operates on a 1.8 V power supply.
All input are 1.8 V compatible. Separate output power (VDDQ)
pins are used to decouple output noise from the internal circuits
and are 1.8 V compatible.
Parameter Synopsis
-333
-300
-250
-200
Unit
Pipeline
3-1-1-1
tKQ
tCycle
2.5
3.0
2.5
3.3
2.5
4.0
3.0
5.0
ns
Curr (x18)
Curr (x32/x36)
245
275
225
250
195
220
165
185
mA
Flow Through
2-1-1-1
tKQ
tCycle
4.5
5.0
5.5
6.5
ns
Curr (x18)
Curr (x32/x36)
195
220
180
200
155
175
140
155
mA
相关PDF资料 |
PDF描述 |
|---|---|
| GS880Z32CGT-250 | 256K X 32 ZBT SRAM, 5.5 ns, PQFP100 |
| GS88118AGT-150I | 512K X 18 CACHE SRAM, 7.5 ns, PQFP100 |
| GS88118AGT-133T | 512K X 18 CACHE SRAM, 8.5 ns, PQFP100 |
| GS88136BD-333 | 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
| GS88136BD-333I | 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
相关代理商/技术参数 |
参数描述 |
|---|---|
| GS880V18BT-300 | 制造商:GSI 制造商全称:GSI Technology 功能描述:512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
| GS880V18BT-300I | 制造商:GSI 制造商全称:GSI Technology 功能描述:512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
| GS880V18BT-333 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 9MBIT 512KX18 4.5NS/2.5NS 100TQFP - Trays |
| GS880V18BT-333I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 9MBIT 512KX18 4.5NS/2.5NS 100TQFP - Trays |
| GS880V32BGT-200 | 制造商:GSI 制造商全称:GSI Technology 功能描述:512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
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