参数资料
型号: GS881Z18BGD-250I
厂商: GSI TECHNOLOGY
元件分类: SRAM
英文描述: 512K X 18 ZBT SRAM, 5.5 ns, PBGA165
封装: 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-165
文件页数: 1/39页
文件大小: 1318K
代理商: GS881Z18BGD-250I
GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
9Mb Pipelined and Flow Through
Synchronous NBT SRAM
333 MHz–150 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
100-Pin TQFP & 165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.06a 2/2008
1/39
2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
User-configurable Pipeline and Flow Through mode
NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
Fully pin-compatible with both pipelined and flow through
NtRAM, NoBL and ZBT SRAMs
IEEE 1149.1 JTAG-compatible Boundary Scan
2.5 V or 3.3 V +10%/–10% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleave Burst mode
Pin-compatible with 2M, 4M, and 18M devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ pin for automatic power-down
JEDEC-standard packages
RoHS-compliant 100-lead TQFP and 165-bump BGA
packages available
Functional Description
The GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
is a 9Mbit Synchronous Static SRAM. GSI's NBT SRAMs,
like ZBT, NtRAM, NoBL or other pipelined read/double late
write or flow through read/single late write SRAMs, allow
utilization of all available bus bandwidth by eliminating the
need to insert deselect cycles when the device is switched from
read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
may be configured by the user to operate in Pipeline or Flow
Through mode. Operating as a pipelined synchronous device,
in addition to the rising-edge-triggered registers that capture
input signals, the device incorporates a rising-edge-triggered
output register. For read cycles, pipelined SRAM output data is
temporarily stored by the edge triggered output register during
the access cycle and then released to the output drivers at the
next rising edge of clock.
The GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
is implemented with GSI's high performance CMOS
technology and is available in a JEDEC-standard 100-pin
TQFP package.
Paramter Synopsis
-333
-300
-250
-200
-150
Unit
Pipeline
3-1-1-1
tKQ
tCycle
2.5
3.0
2.5
3.3
2.5
4.0
3.0
5.0
3.8
6.7
ns
Curr (x18)
Curr (x32/x36)
250
290
230
265
200
230
170
195
140
160
mA
Flow Through
2-1-1-1
tKQ
tCycle
4.5
5.0
5.5
6.5
7.5
ns
Curr (x18)
Curr (x32/x36)
200
230
185
210
160
185
140
160
128
145
mA
Not
Recommended
for
New
Design
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