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参数资料
| 型号： | GT-64012 |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Secondary Cache Controller For the MIPS R4600/4650/4700/5000,(用于MIPS R4600/4650/4700/5000处理器的二级高速缓存控制器) |
| 中文描述： | 二级高速缓存控制器（用于MIPS的R4600/4650/4700/5000处理器的二级高速缓存控制器的MIPS R4600/4650/4700/5000） |
| 文件页数： | 18/24页 |
| 文件大小： | 614K |
| 代理商： | GT-64012 |
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The GT-64012 distinguishes between two types of Reads: uncacheable (partial reads) and cacheable (block reads).
All partial reads (SysCmd[7:5] = 0 and SysCmd[3] = 1), are forwarded to the System a cycle later than the issue cycle
on the CPU bus. As both the SysAD and SysCmd buses are point-to-point connections between the CPU and the Sys-
tem, a newly designed System ASIC may monitor SysCmd, ValidOut*, TagOp0, and TagOp1 to detect a partial read
request. When a partial read is detected, with both TagOp0 and TagOp1 inactive, the System ASIC may start process-
ing the transaction immediately, knowing that a cycle later it should ignore the GValidOut* generated by the GT-64012.
One cycle is therefore saved.
Block reads are checked by the GT-64012 for Hit or Miss in the Tag SRAM. The lookup is done one cycle after Valid-
Out* is asserted. No action is taken by the GT-64012 until the CPU bus is released (read issue cycle). One cycle after
the CPU bus is released the GT-64012 asserts GValidOut* if the lookup turned to be a Miss so as to forward the
request to the system.
A newly designed System ASIC may monitor the Hit signal during the look-up phase to determine in advance if the
request will be forwarded to the system or not. If a Hit occurs, no action should be taken as data will be returned from
the secondary cache. If a Miss occurs, the System ASIC may start processing the request ignoring the GValidOut*
which will be generated by the GT-64012 at least a cycle later. Care should be taken to keep track over CPU bus status
(released or not) before SysAD and SysCmd get driven by the System; i.e., GRelease* should be monitored for asser-
tion before SysCmd and SysAD are truly released. In systems where RdRdy* is constantly asserted, GRelease* will be
asserted two cycles after the issue cycle.
In most systems, RdRdy* is constantly asserted or even tied to ground so the same cycle in which ValidOut* is firstly
asserted is also the issue cycle. Such systems may simplify the decision making involved in this process.
The GT-64010 System Controller from Galileo takes advantage of this methodology to provide a system designer with
maximum performance when also using the GT-64012 Secondary Cache Controller.
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It is possible to utilize a simple software mechanism to determine if a GT-64012 is present in the system or not. The
sequence of transactions to be made is as follows (all are addressed to the same cache line):
1. cacheable read (block);
2. first level cache invalidate (cache operation)
or two first level cache line replacements;
3. uncacheable write;
4. cacheable read.
If the returned data from step 4 is updated by the written data in step 3, the GT-64012 is not present in the system,
and vice versa.
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It is easy to interface the 5V GT-64012 to a 3.3V CPU subsystem. The block diagram that appears on the cover needs
to be augmented only by one component. The existing components are already 3.3V-compatible.
The burst synchronous SRAMs are available in 3.3V Vcc versions with 5V-tolerant inputs and thus can interface directly
to the GT-64012.
Tag SRAMs like the IDT71215 can have their I/Os working from a 5V or 3.3V source, while the supplied Vcc is 5V, and
thus can work in a mixed voltage environment.
The FCT163501 3.3V bidirectional latches can be used instead of the 5V version, since their inputs are still 5V tolerant.
The QuickSwitches used to gate the ValidOut and ValidIn signals provide an effective mechanism to interface between
5V and 3.3V.
Consequently, the only extra component needed is another QuickSwitch to interface the GT-64012 outputs ExtReq*
and GRelease*, plus the I/Os SysCmd[8:3], to the 3.3V subsystem. The QS3384 when supplied with 4.3V works as an
effective 5V to 3.3V converter with zero delay. This is illustrated in the figure below.
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| GT5-2/1S-HU | RECTANGULAR CONNECTOR |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| GT64115-A2-PBB-C000 | 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000 |
| GT-64120A-B-0 | 制造商:GALILEO 功能描述: |
| GT-64120A-B2 | 制造商:GALILEO 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Galileo Corp 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Marvell 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA |
| GT64120AB2-BBB1C000 | 制造商:Marvell 功能描述:64-BIT MIPS SYSTEM CONTROLLER W/ 2 X 32-BIT OR 1 X 64-BIT/6 - Trays |
| GT64120AB2-BBB1C083 | 制造商:Marvell 功能描述:Marvell GT64120AB2-BBB1C083 |
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