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参数资料
| 型号： | HCPL0600V |
| 厂商： | Fairchild Optoelectronics Group |
| 文件页数： | 5/18页 |
| 文件大小： | 0K |
| 描述： | OPTOCOUPLER 10MBIT SGL 8-SOIC |
| 标准包装： | 3,000 |
| 电压 - 隔离： | 3750Vrms |
| 通道数： | 1，单向 |
| 电流 - 输出 / 通道： | 50mA |
| 数据速率： | 10Mbps |
| 电流 - DC 正向(If)： | 50mA |
| 输入类型： | DC |
| 输出类型： | 开路集电极 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SO |
| 包装： | 管件 |
Transfer Characteristics (T A = -40°C to +85°C unless otherwise speci?ed.)
Symbol
I OH
V OL
I FT
DC Characteristics
High Level Output Current
Low Level Output Voltage
Input Threshold Current
Test Conditions
V CC = 5.5V, V O = 5.5 V, I F = 250μA,
V E = 2.0V (2)
V CC = 5.5V, I F = 5mA, V E = 2.0V,
I OL = 13mA (2)
V CC = 5.5V, V O = 0.6V, V E = 2.0V,
Min.
Typ.*
Max.
100
0.6
5
Unit
μA
V
mA
I OL = 13mA
Isolation Characteristics (T A = -40°C to +85°C unless otherwise speci?ed.)
Symbol
I I-O
Characteristics
Input-Output
Test Conditions
Relative humidity = 45%,
Min.
Typ.*
Max.
1.0*
Unit
μA
Insulation Leakage Current
T A = 25°C, t = 5s,
V I-O = 3000 VDC (11)
V ISO
R I-O
Withstand Insulation Test Voltage
Resistance (Input to Output)
R H < 50%, T A = 25°C,
I I-O ≤ 2μA, t = 1 min. (11)
V I-O = 500V (11)
3750
10 12
V RMS
Ω
C I-O
Capacitance (Input to Output)
f=
1MHz (11)
0.6
pF
*All typical values are at V CC = 5 V, T A = 25°C
Notes:
1. The V CC supply to each optoisolator must be bypassed by a 0.1μF capacitor or larger. This can be either a ceramic
or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible
to the package V CC and GND pins of each device.
2. Enable Input – No pull up resistor required as the device has an internal pull up resistor.
3. t PLH – Propagation delay is measured from the 3.75mA level on the HIGH to LOW transition of the input current
pulse to the 1.5V level on the LOW to HIGH transition of the output voltage pulse.
4. t PHL – Propagation delay is measured from the 3.75mA level on the LOW to HIGH transition of the input current
pulse to the 1.5V level on the HIGH to LOW transition of the output voltage pulse.
5. t r – Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.
6. t f – Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.
7. t ELH – Enable input propagation delay is measured from the 1.5V level on the HIGH to LOW transition of the input
voltage pulse to the 1.5V level on the LOW to HIGH transition of the output voltage pulse.
8. t EHL – Enable input propagation delay is measured from the 1.5V level on the LOW to HIGH transition of the input
voltage pulse to the 1.5V level on the HIGH to LOW transition of the output voltage pulse.
9. CM H – The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high
state (i.e., V OUT > 2.0V). Measured in volts per microsecond (V/μs).
10. CM L – The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the low
output state (i.e., V OUT < 0.8V). Measured in volts per microsecond (V/μs).
11. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together, and Pins 5, 6, 7 and 8 shorted
together.
?2006 Fairchild Semiconductor Corporation
HCPL06XX Rev. 1.0.9
5
www.fairchildsemi.com
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