- 您现在的位置：买卖IC网 > PDF目录371784 > HCTL-2032 Quadrature Decoder/Counter Interface ICs PDF资料下载
参数资料
| 型号： | HCTL-2032 |
| 元件分类： | 通用总线功能 |
| 英文描述： | Quadrature Decoder/Counter Interface ICs |
| 中文描述： | 正交解码器/计数器接口芯片 |
| 文件页数： | 15/20页 |
| 文件大小： | 302K |
| 代理商： | HCTL-2032 |
15
Position Data Latch
The position data latch is a 32-
bit latch which captures the
position counter output data on
each rising clock edge, except
when its inputs are disabled by
the inhibit logic section during
four-byte read operations. The
output data is passed to the bus
interface section. When active, a
signal from the inhibit logic
section prevents new data from
being captured by the latch,
keeping the data stable while
successive reads are made
through the bus section. The
latch is automatically re-enabled
at the end of these reads. The
latch is cleared to 0
asynchronously by the RST
signal.
Inhibit Logic
The Inhibit Logic Section
samples the OE, SEL1 and SEL2
signals on the falling edge of
the clock and, in response to
certain conditions (see Figure
15), inhibits the position data
latch. The RST signal
asynchronously clears the
inhibit logic, enabling the latch.
Bus Interface
The bus interface section
consists of a 32 to 8 line
multiplexer and an 8-bit, three-
state output buffer. The
multiplexer allows independent
access to the low and high bytes
of the position data latch. The
SEL1, SEL2 and OE signals
determine which byte is output
and whether or not the output
bus is in the high-Z state. In
the HCTL-20XX-XX, the data
latch is 32 bit wide.
Quadrature Decoder Output
(HCTL-2032 / 2032-SC only)
The quadrature decoder output
section consists of count and
up/down outputs derived from
the 4x/2x/1x decoder mode of
the HCTL-2032 / 2032-SC.
When the decoder has detected
a count, a pulse, one-half clock
cycle long, will be output on the
CNT
DCDR
pin. This output will
occur during the clock cycle in
which the internal counter is
updated. The U/D pin will be
set to the proper voltage level
one clock cycle before the rising
edge of the CNT
DCDR
pulse, and
held one clock cycle after the
rising edge of the CNT
DCDR
pulse. These outputs are not
affected by the inhibit logic.
Cascade Output
(HCTL-2032 / 2032-SC only)
The cascade output also consists
of count and up/down outputs.
When the HCTL-2032 / 2032-SC
internal counter overflows or
underflows, a pulse, one-half
clock cycle long, will be output
on the CNT
CAS
pin. This output
will occur during the clock cycle
in which the internal counter is
updated. The U/D pin will be
set to the proper voltage level
one clock cycle before the rising
edge of the CNT
CAS
pulse, and
held one clock cycle after the
rising edge of the CNT
CAS
pulse.
These outputs are not affected
by the inhibit logic.
Figure 15. Four Bytes Read Sequence
Step
1
SEL1
L
SEL2
H
OE
L
CLK
Inhibit Signal Action
1
Set inhibit; Read MSB
2
H
H
L
1
Read 2
nd
Byte
3
L
L
L
1
Read 3
rd
Byte
4
H
L
L
1
Read LSB
5
X
X
H
0
Completes inhibit logic reset
相关PDF资料 |
PDF描述 |
|---|---|
| HCTL-2032-SC | Quadrature Decoder/Counter Interface ICs |
| HCTS00D | Radiation Hardened Quad 2-Input NAND Gate |
| HCTS00HMSR | Radiation Hardened Quad 2-Input NAND Gate |
| HCTS00DMSR | Radiation Hardened Quad 2-Input NAND Gate |
| HCTS00K | Radiation Hardened Quad 2-Input NAND Gate |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HCTL-2032-SC | 功能描述:接口 - 专用 Decoder/Counter RoHS:否 制造商:Texas Instruments 产品类型:1080p60 Image Sensor Receiver 工作电源电压:1.8 V 电源电流:89 mA 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:BGA-59 |
| HCTL-2032-SCT | 制造商:Avago Technologies 功能描述:QUADRATURE DECODER/ COUNTER INTRFC IC 32PIN - Tape and Reel |
| HCT-L-R5A | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Optoelectronic |
| HCT-L-R5B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Optoelectronic |
| HCT-L-R-HA | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Optoelectronic |
发布紧急采购，3分钟左右您将得到回复。