参数资料
| 型号： | HD3-4702-9Z |
| 厂商： | Intersil |
| 文件页数： | 4/8页 |
| 文件大小： | 0K |
| 描述： | IC BIT RATE GEN CMOS 16-PDIP |
| 标准包装： | 250 |
| 类型： | 比特率发生器 |
| PLL： | 无 |
| 输入： | 时钟，晶体 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 1MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 16-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 16-PDIP |
| 包装： | 管件 |
4
FN2954.2
August 24, 2006
Application Information
Single Channel Bit Rate Generator
Figure 1 shows the simplest application of the HD-4702. This
circuit generates one of five possible bit rates as determined by
the setting of a single pole, 5-position switch. The Bit Rate Out-
put (Z) drives one standard TTL load or four low power Schot-
tky loads over the full temperature range. The possible output
frequencies correspond to 110, 150, 300, 1200, and 2400
Baud. For many low cost terminals, these five bit rates are ade-
quate.
FIGURE 1. SWITCH SELECTABLE BIT RATE GENERATOR
CONFIGURATION PROVIDING FIVE BIT RATES
Simultaneous Generation of Several Bit Rates
Figure 2 shows a simple scheme that generates eight bit rates
on eight output lines, using one HD-4702 and one 93L34 Bit
Addressable Latch. This and the following applications take
advantage of the built-in scan counter (prescaler) outputs. As
shown in the block diagram, these outputs (Q0 to Q2) go
through a complete sequence of eight states for every half-
period of the highest output frequency (9600 Baud). Feeding
these Scan Counter Outputs back to the Select Inputs of the
multiplexer causes the HD-4702 to interrogate sequentially
eight different frequency signals. The 93L34 8-bit addressable
Latch, addressed by the same Scan Counter Outputs, re-con-
verts the multiplexed single Output (Z) of the HD-4702 into
eight parallel output frequency signals. In the simple scheme of
Figure 2, input S3 is left open (HIGH) and the following bit rates
are generated:
Other bit rate combinations can be generated by changing the
Scan Counter to Selector interconnection or by inserting logic
gates into this path.
19200 Baud Operation
Though a 19200 Baud signal is not internally routed to the mul-
tiplexer, the HD-4702 can be used to generate this bit rate by
connecting the Q2 output to IM input and applying select code.
An additional 2-input NOR gate can be used to retain the “Zero
Baud” feature on select code 1 for the HD-4702 (See Figure 3).
SWITCH POSITION
HD-4702 BIT RATE
1
110 Baud
2
150 Baud
3
300 Baud
4
1200 Baud
5
2400 Baud
Q0: 110 Baud
Q1: 9600 Baud
Q2: 4800 Baud
Q3: 1800 Baud
Q4: 1200 Baud
Q5: 2400 Baud
Q6: 300 Baud
Q7: 150 Baud
HD-4702
IM
S0
S1
S2
S3
CP
ECP
IX
OX
CO
Q0
Q1
Q2
Z
OUTPUT
SPST SWITCH
2.4576 MHz
CRYSTAL
10M
56pF
2
1
34
5
See Table 1.
TABLE 1. CRYSTAL SPECIFICATIONS
PARAMETERS
TYPICAL CRYSTAL SPEC
Frequency
2.4576MHz “AT” Cut
Series Resistance (Max)
250
Unwanted Modes
-6.0dB (Min)
Type of Operation
Parallel
Load Capacitance
32pF +0.5
HD-4702
IM
S0
S1
S2
S3
CP
ECP
IX
OX
CO
Q0
Q1
Q2
Z
2.4576 MHz
CRYSTAL
10M
56pF
CL Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
A0
A1
A2
960
0
11
0
480
0
180
0
120
0
240
0
300
150
93L34
E
D
See Table 1.
FIGURE 2. BIT RATE GENERATOR CONFIGURATION WITH
EIGHT SIMULTANEOUS FREQUENCIES
HD-4702
IM
S0
S1
S2
S3
CP
ECP
IX
OX
CO
Q0
Q1
Q2
Z
OUTPUT
2.4576 MHz
CRYSTAL
10M
56pF
See Table 1.
FIGURE 3. 19200 BAUD OPERATION
HD-4702
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