参数资料
| 型号： | HD3-4702-9Z |
| 厂商： | Intersil |
| 文件页数： | 6/8页 |
| 文件大小： | 0K |
| 描述： | IC BIT RATE GEN CMOS 16-PDIP |
| 标准包装： | 250 |
| 类型： | 比特率发生器 |
| PLL： | 无 |
| 输入： | 时钟，晶体 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 1MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 16-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 16-PDIP |
| 包装： | 管件 |
6
FN2954.2
August 24, 2006
Electrical Specifications
VCC = 5V ±10%, TA = -40
oC to +85oC (HD-4702-9), T
A = -55
oC to +125oC (HD-4702-8)
SYMBOL
AC PARAMETER
LIMITS
UNITS
TEST
CONDITIONS
MIN
MAX
tPLH
Propagation Delay, IX to CO
-
350
ns
VCC = 4.5V
CL ≤ 7pF on OX
CL = 50pF
(Note 1)
tPHL
-
275
ns
tPLH
Propagation Delay, CP to CO
-
260
ns
tPHL
-
220
ns
tPLH
Propagation Delay, CO to Qn
-
(Note 2)
ns
tPHL
-
(Note 2)
ns
tPLH
Propagation Delay, CO to Z
-
85
ns
tPHL
-75
ns
tTLH
Output Transition Time (Except OX)
-
160
ns
tTHL
-75
ns
ts
Set-Up Time, Select to CO
350
-
ns
th
Hold Time, Select to CO
0
-
ns
ts
Set-Up Time, IM to CO
350
-
ns
th
Hold Time, IM to CO
0
-
ns
twCP(L)
Minimum Clock Pulse Width, Low (Notes 3, 4)
120
-
ns
twCP(H)
Minimum Clock Pulse Width, High (Notes 3, 4)
120
-
ns
twCP(L)
Minimum IX Pulse Width, Low (Note 4)
160
-
ns
twCP(H)
Minimum IX Pulse Width, High (Note 4)
160
-
ns
tPLH
Propagation Delay IX to CO
-
300
ns
VCC = 4.5V
CL ≤ 7pF on OX
CL = 15pF
(Note 1)
tPHL
-
250
ns
tPLH
Propagation Delay CP to CO
-
215
ns
tPHL
-
195
ns
tPLH
Propagation Delay CO to Qn
-
(Note 2)
ns
tPHL
-
(Note 2)
ns
tPLH
Propagation Delay CO to Z
-
75
ns
tPHL
-65
ns
tTLH
Output Transition Time (Except OX)
-
80
ns
tTHL
-40
ns
NOTES:
1. Propagation Delays (tPLH and tPHL) and Output Transition Times (tTLH and tTHL) will change with Output Load Capacitance (CL). Setup Times
(ts), Hold Times (th), and Minimum Pulse Widths (tw) do not vary with load capacitance.
2. For multichannel operation, Propagation Delay (CO to Qn) plus Set-Up Time, Select to CO, is guaranteed to be
≤ 367ns.
3. The first High Level Clock Pulse after ECP goes Low must be at least 350ns long to guarantee reset of all Counters.
4. It is recommended that input rise and fall times to the clock inputs (CP, IX) be less than 15ns.
HD-4702
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