![](http://datasheet.mmic.net.cn/200000/HD4074394S_datasheet_15067156/HD4074394S_109.png)
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4.5.5
Interrupt Handling Sequence
Interrupts are controlled by the interrupt controller. Figure 4-1 shows the block diagram of the
interrupt controller, and tables 4-5 (a) and 4-5 (b) list the activation conditions for interrupt
handling. Figures 4-2 and 4-3 show the flowcharts for the sequences up to the point where an
interrupt is accepted. The interrupt handling sequence is described below.
1. When an interrupt occurs and the interrupt request flag (IF) is set to 1 in the state where the
corresponding interrupt mask (IM) is cleared to 0, an interrupt signal is sent to the priority
controller.
2. The priority controller selects the interrupt with the highest priority and defers the other
interrupts.
3. Next the interrupt controller checks the interrupt enable flag (IE). If IE is 1, the highest priority
interrupt is accepted, but if IE is 0, all interrupts are deferred.
4. When an interrupt is accepted, the interrupt controller waits for the execution of the current
instruction to complete. At that point, the values of the program counter (PC), the carry (CA),
and the status (ST) are saved on the stack and the stack pointer is decremented by 4.
5. IE is cleared to 0. This disables all interrupts.
6. The interrupt controller generates the vector address corresponding to the accepted interrupt
and loads that value into the PC. Execution of the interrupt handler starts at the branch
destination of the JMPL instruction stored at the vector address. (The user must code a JMPL
instruction to the start of the corresponding interrupt handler at each vector address.)