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Contents
Section 1 Overview ..............................................................................................................
1
1.1
Overview ............................................................................................................................
1
1.2
Internal Block Diagrams .................................................................................................... 10
1.3
Pin Functions...................................................................................................................... 17
1.3.1
HD404344R and HD404394 Series Pin Functions ............................................... 17
1.3.2
HD404318/HD404358/HD404358R Series Pin Functions................................... 23
1.3.3
HD404339/HD404369 Series Pin Functions ........................................................ 31
Section 2 Memory................................................................................................................. 39
2.1
Overview ............................................................................................................................ 39
2.2
ROM ................................................................................................................................... 40
2.2.1
Vector Address Area ............................................................................................. 40
2.2.2
Zero Page Subroutine Area ................................................................................... 40
2.2.3
Pattern Area........................................................................................................... 40
2.2.4
Program Area ........................................................................................................ 41
2.3
RAM ................................................................................................................................... 43
2.3.1
RAM Mapped Register Area ................................................................................ 48
2.3.2
Memory Register Area.......................................................................................... 57
2.3.3
Data Area .............................................................................................................. 58
2.3.4
Stack Area ............................................................................................................. 59
Section 3 CPU........................................................................................................................ 61
3.1
Overview ............................................................................................................................ 61
3.1.1
Features ................................................................................................................. 61
3.1.2
Address Space ....................................................................................................... 62
3.1.3
Register Organization............................................................................................ 63
3.2
CPU Registers .................................................................................................................... 64
3.2.1
Accumulator (A) and B Register (B) .................................................................... 64
3.2.2
W Register (W), X Register (X), and Y Register (Y) ........................................... 64
3.2.3
SPX Register (SPX), SPY Register (SPY)............................................................ 64
3.2.4
Carry Flag (CA) .................................................................................................... 64
3.2.5
Status Flag (ST) .................................................................................................... 64
3.2.6
Program Counter (PC) .......................................................................................... 64
3.2.7
Stack Pointer (SP) ................................................................................................. 65
3.3
Addressing Modes.............................................................................................................. 65
3.3.1
RAM Addressing Modes ...................................................................................... 65
3.3.2
ROM Addressing Modes and the P Instruction .................................................... 67
3.4
Processing States ................................................................................................................ 70
3.4.1
Overview ............................................................................................................... 70