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Section 16 I
2C Bus Interface [H8S/2138 Series Option]
A two-channel I
2C bus interface is available as an option in the H8S/2138 Series. The I2C bus
interface is not available for the H8S/2134 Series. Observe the following notes when using this
option.
1. For mask-ROM versions, a W is added to the part number in products in which this optional
function is used.
Examples: HD6432137WF
2. The product number is identical for F-ZTAT versions. However, be sure to inform your
Hitachi sales representative if you will be using this option.
16.1
Overview
A two-channel I
2C bus interface is available for the H8S/2138 Series as an option. The I2C bus
interface conforms to and provides a subset of the Philips I
2C bus (inter-IC bus) interface
functions. The register configuration that controls the I
2C bus differs partly from the Philips
configuration, however.
Each I
2C bus interface channel uses only one data line (SDA) and one clock line (SCL) to
transfer data, saving board and connector space.
16.1.1
Features
Selection of addressing format or non-addressing format
I2C bus format: addressing format with acknowledge bit, for master/slave operation
Serial format: non-addressing format without acknowledge bit, for master operation only
Conforms to Philips I2C bus interface (I2C bus format)
Two ways of setting slave address (I2C bus format)
Start and stop conditions generated automatically in master mode (I2C bus format)
Selection of acknowledge output levels when receiving (I2C bus format)
Automatic loading of acknowledge bit when transmitting (I2C bus format)
Wait function in master mode (I2C bus format)
A wait can be inserted by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait can be cleared by clearing the interrupt flag.
Wait function in slave mode (I2C bus format)
A wait request can be generated by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait request is cleared when the next transfer becomes possible.
Three interrupt sources