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2.8.5
Bus-Released State
This is a state in which the bus has been released in response to a bus request from a bus master
other than the CPU. While the bus is released, the CPU halts except for internal operations.
There is one other bus master in addition to the CPU: the data transfer controller (DTC).
For further details, refer to section 6, Bus Controller.
2.8.6
Power-Down State
The power-down state includes both modes in which the CPU stops operating and modes in
which the CPU does not stop. There are five modes in which the CPU stops operating: sleep
mode, software standby mode, hardware standby mode, subsleep mode, and watch mode. There
are also three other power-down modes: medium-speed mode, module stop mode, and subactive
mode. In medium-speed mode, the CPU and other bus masters operate on a medium-speed
clock. Module stop mode permits halting of the operation of individual modules, other than the
CPU. Subactive mode, subsleep mode, and watch mode are power-down modes that use
subclock input. For details, refer to section 23, Power-Down State.
Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the
software standby bit (SSBY) in the standby control register (SBYCR) and the LSON bit in the
low-power control register (LPWRCR) are both cleared to 0. In sleep mode, CPU operations
stop immediately after execution of the SLEEP instruction. The contents of CPU registers are
retained.
Software Standby Mode: A transition to software standby mode is made if the SLEEP
instruction is executed while the SSBY bit in SBYCR is set to 1 and the LSON bit in LPWRCR
and the PSS bit in the WDT1 timer control/status register (TCSR) are both cleared to 0. In
software standby mode, the CPU and clock halt and all MCU operations stop. As long as a
specified voltage is supplied, the contents of CPU registers and on-chip RAM are retained. The
I/O ports also remain in their existing states.
Hardware Standby Mode: A transition to hardware standby mode is made when the
67%< pin
goes low. In hardware standby mode, the CPU and clock halt and all MCU operations stop. The
on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip
RAM contents are retained.