406
; Execute erase-verify
EVR:
MOV.W
#RAMSTR,
R2
; Starting transfer destination address (RAM)
MOV.W
#ERVADR,
R3
;
ADD.W
R3,
R2
; #RAMSTR + #ERVADR
→ R2
MOV.W
#START,
R3
;
SUB.W
R3,
R2
; Address of data area used in RAM
MOV.B
#H'00,
R1L
; Used to test R1L bit in R0
MOV.B
#H'b,
R4H
; Set erase-verify loop counter
BSET
#3,
@FLMCR:8
; Set EV bit
LOOPEV:
DEC
R4H
;
BNE
LOOPEV
; Wait loop
EBRTST:
CMP.B
#H'0C,
R1L
; R1L = H'0C?
BEQ
HANTEI
; If finished checking all R0 bits, branch to HANTEI
CMP.B
#H'08,
R1L
;
BMI
EBR2EV
; Test EBR1 if R1L
≥ 8, or EBR2 if R1L < 8
MOV.B
R1L,
R1H
;
SUBX
#H'08,
R1H
; R1L – 8
→ R1H
BTST
R1H,
R0H
; Test R1H bit in EBR1 (R0H)
BNE
ERSEVF
; If R1H bit in EBR1 (R0H) is 1, branch to ERSEVF
BRA
ADD01
; If R1H bit in EBR1 (R0H) is 0, branch to ADD01
EBR2EV:
BTST
R1L,
R0L
; Test R1L bit in EBR2 (R0L)
BNE
ERSEVF
; If R1L bit in EBR2 (R0H) is 1, branch to ERSEVF
ADD01:
INC
R1L
; R1L + 1
→ R1L
MOV.W
@R2+,
R3
; Dummy-increment R2
BRA
EBRTST
;
ERASE1:
BRA
ERASE
; Branch to ERASE via Erase 1
ERSEVF:
MOV.W
@R2+,
R3
; Top address of block to be erase-verified
EVR2:
MOV.B
#H'FF,
R1H
;
MOV.B
R1H,
@R3
; Dummy write
MOV.B
#H'c,
R4H
; Set erase-verify loop counter
LOOPEP:
DEC
R4H
;
BNE
LOOPEP
; Wait loop
MOV.B
@R3+,
R1H
; Read
CMP.B
#H'FF,
R1H
; Read data = H'FF?
BNE
BLKAD
; If read data
≠ H'FF branch to BLKAD
MOV.W
@R2,
R4
; Top address of next block
CMP.W
R4,
R3
; Last address of block?
BNE
EVR2
CMP.B
#H'08,
R1L
BMI
SBCLR
; Test EBR1 if R1L
≥ 8, or EBR2 if R1L < 8
MOV.B
R1L,
R1H
;
SUBX
#H'08,
R1H
; R1L – 8
→ R1H
BCLR
R1H,
R0H
; Clear R1H bit in EBR1 (R0H)
BRA
BLKAD
SBCLR:
BCLR
R1L,
R0L
; Clear R1L bit in EBR2 (R0L)
BLKAD:
INC
R1L
; R1L + 1
→ R1L
BRA
EBRTST
;
HANTEI:
BCLR
#3,
@FLMCR:8
; Clear EV bit
MOV.W
R0,
@EBR1
;
BEQ
EOWARI
; If EBR1/EBR2 is all 0, erasing ended normally