- 您现在的位置：买卖IC网 > PDF目录299170 > HD6433837L 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PQFP100 PDF资料下载
参数资料
| 型号： | HD6433837L |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 98/194页 |
| 文件大小： | 2303K |
| 代理商： | HD6433837L |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页当前第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页第190页第191页第192页第193页第194页
187
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
19.8.3
Receive Compete Flag and Interrupt
The USART Receiver has one flag that indicates the Receiver state.
The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buf-
fer. This flag is one when unread data exist in the receive buffer, and zero when the receive
buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXENn = 0),
the receive buffer will be flushed and consequently the RXCn bit will become zero.
When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USART Receive
Complete interrupt will be executed as long as the RXCn Flag is set (provided that global inter-
rupts are enabled). When interrupt-driven data reception is used, the receive complete routine
must read the received data from UDRn in order to clear the RXCn Flag, otherwise a new inter-
rupt will occur once the interrupt routine terminates.
19.8.4
Receiver Error Flags
The USART Receiver has three Error Flags: Frame Error (FEn), Data OverRun (DORn) and
Parity Error (UPEn). All can be accessed by reading UCSRnA. Common for the Error Flags is
that they are located in the receive buffer together with the frame for which they indicate the
error status. Due to the buffering of the Error Flags, the UCSRnA must be read before the
receive buffer (UDRn), since reading the UDRn I/O location changes the buffer read location.
Another equality for the Error Flags is that they can not be altered by software doing a write to
the flag location. However, all flags must be set to zero when the UCSRnA is written for upward
compatibility of future USART implementations. None of the Error Flags can generate interrupts.
The Frame Error (FEn) Flag indicates the state of the first stop bit of the next readable frame
stored in the receive buffer. The FEn Flag is zero when the stop bit was correctly read (as one),
and the FEn Flag will be one when the stop bit was incorrect (zero). This flag can be used for
detecting out-of-sync conditions, detecting break conditions and protocol handling. The FEn
Flag is not affected by the setting of the USBSn bit in UCSRnC since the Receiver ignores all,
except for the first, stop bits. For compatibility with future devices, always set this bit to zero
when writing to UCSRnA.
The Data OverRun (DORn) Flag indicates data loss due to a receiver buffer full condition. A
Data OverRun occurs when the receive buffer is full (two characters), it is a new character wait-
ing in the Receive Shift Register, and a new start bit is detected. If the DORn Flag is set there
was one or more serial frame lost between the frame last read from UDRn, and the next frame
read from UDRn. For compatibility with future devices, always write this bit to zero when writing
to UCSRnA. The DORn Flag is cleared when the frame received was successfully moved from
the Shift Register to the receive buffer.
The Parity Error (UPEn) Flag indicates that the next frame in the receive buffer had a Parity
Error when received. If Parity Check is not enabled the UPEn bit will always be read zero. For
compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more
details see ”Parity Bit Calculation” on page 180 and ”Parity Checker” on page 187.
19.8.5
Parity Checker
The Parity Checker is active when the high USART Parity mode (UPMn1) bit is set. Type of Par-
ity Check to be performed (odd or even) is selected by the UPMn0 bit. When enabled, the Parity
Checker calculates the parity of the data bits in incoming frames and compares the result with
the parity bit from the serial frame. The result of the check is stored in the receive buffer together
相关PDF资料 |
PDF描述 |
|---|---|
| HD6433837SH | 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PQFP100 |
| HD64463 | MULTIFUNCTION PERIPHERAL, PBGA387 |
| HD6473258CP10 | 8-BIT, OTPROM, MICROCONTROLLER, PQCC68 |
| HD74AC174T | D FLIP-FLOP, PDSO16 |
| HD74HC149FP | HC/UH SERIES, 8-BIT ENCODER, PDSO20 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HD6433837S | 制造商:未知厂家 制造商全称:未知厂家 功能描述:H8/3834 Series H8/3837 HD6433837.HD6433837S.HD64473837. H8/3836 HD6433836.HD6433836S H8/3835 HD6433835.HD6433835S H8/3834 HD6433834.HD633834S.HD6473834 H8/3833 HD6433833.HD6433833S H8/3832 HD6433832S Hardware Manual |
| HD6433837SD | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:single-chip microcomputers |
| HD6433837SE | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:single-chip microcomputers |
| HD6433837SF | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:single-chip microcomputers |
| HD6433837SH | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:single-chip microcomputers |
发布紧急采购，3分钟左右您将得到回复。