参数资料
型号: HFA1135IBZ
厂商: Intersil
文件页数: 11/15页
文件大小: 0K
描述: IC OPAMP CFA 360MHZ LP 8-SOIC
标准包装: 98
应用: 电流反馈
电路数: 1
-3db带宽: 360MHz
转换速率: 1530 V/µs
电流 - 电源: 6.9mA
电流 - 输出 / 通道: 60mA
电压 - 电源,单路/双路(±): ±4.5 V ~ 5.5 V
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
产品目录页面: 1234 (CN2011-ZH PDF)
5
problems due to the feedback impedance decrease at higher
frequencies). At higher gains the amplifier is more stable, so
RF can be decreased in a trade-off of stability for bandwidth.
The table below lists recommended RF values, and the
expected bandwidth, for various closed loop gains.
Non-inverting Input Source Impedance
For best operation, the DC source impedance seen by the
non-inverting input should be
≥50. This is especially
important in inverting gain configurations where the non-
inverting input would normally be connected directly to GND.
Pulse Undershoot and Asymmetrical Slew Rates
The HFA1135 utilizes a quasi-complementary output stage
to achieve high output current while minimizing quiescent
supply current. In this approach, a composite device
replaces the traditional PNP pulldown transistor. The
composite device switches modes after crossing 0V,
resulting in added distortion for signals swinging below
ground, and an increased undershoot on the negative
portion of the output waveform (see Figures 9, 13, and 17).
This undershoot isn’t present for small bipolar signals, or
large positive signals. Another artifact of the composite
device is asymmetrical slew rates for output signals with a
negative voltage component. The slew rate degrades as the
output signal crosses through 0V (see Figures 9, 13, and
17), resulting in a slower overall negative slew rate. Positive
only signals have symmetrical slew rates as illustrated in the
large signal positive pulse response graphs (see Figures 7,
11, and 15).
PC Board Layout
This amplifier’s frequency response depends greatly on the
care taken in designing the PC board. The use of low
inductance components such as chip resistors and chip
capacitors is strongly recommended, while a solid
ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10
F) tantalum in parallel with a small value
(0.1
F) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
Care must also be taken to minimize the capacitance to
ground at the amplifier’s inverting input (-IN), as this
capacitance causes gain peaking, pulse overshoot, and if
large enough, instability. To reduce this capacitance, the
designer should remove the ground plane under traces
connected to -IN, and keep connections to -IN as short as
possible.
An example of a good high frequency layout is the
Evaluation Board shown in Figure 2.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line degrade the amplifier’s phase
margin resulting in frequency response peaking and possible
oscillations. In most cases, the oscillation can be avoided by
placing a resistor (RS) in series with the output prior to the
capacitance.
Figure 1 details starting points for the selection of this
resistor. The points on the curve indicate the RS and CL
combinations for the optimum bandwidth, stability, and
settling time, but experimental fine tuning is recommended.
Picking a point above or to the right of the curve yields an
overdamped response, while points below or left of the curve
indicate areas of underdamped performance.
RS and CL form a low pass network at the output, thus
limiting system bandwidth well below the amplifier bandwidth
of 660MHz (AV = +1). By decreasing RS as CL increases (as
illustrated by the curves), the maximum bandwidth is
obtained without sacrificing stability. In spite of this,
bandwidth still decreases as the load capacitance increases.
For example, at AV = +1, RS = 50, CL = 20pF, the overall
bandwidth is 170MHz, but the bandwidth drops to 45MHz at
AV =+1, RS = 10, CL = 330pF.
TABLE 1. OPTIMUM FEEDBACK RESISTOR
GAIN
(AV)RF ()
BANDWIDTH
(MHz)
-1
330
290
+1
1.5k
660
+2
250
330
360
315
+5
180
200
+10
250
90
R
S
(
)
LOAD CAPACITANCE (pF)
50
45
40
35
30
25
20
15
10
5
0
40
80
120
160
200
240
280
320
360
400
AV = +1
AV = +2, RF = 250
FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD
CAPACITANCE
AV = +1
HFA1135
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