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参数资料
| 型号： | HFA3860AIV96 |
| 厂商： | INTERSIL CORP |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | Circular Connector; No. of Contacts:5; Series:MS27473; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:10-5 RoHS Compliant: No |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48 |
| 封装： | 7 X 7 X 1 MM, PLASTIC, TQFP-48 |
| 文件页数： | 18/39页 |
| 文件大小： | 251K |
| 代理商： | HFA3860AIV96 |
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2-148
Acquisition Signal Quality Parameters
Two measures of signal quality are used to determine
acquisition. The first method of determining signal presence is
to measure the correlator output (or bit sync) amplitude. This
measure, however, flattens out in the range of high BER and
is sensitive to signal amplitude. The second measure is phase
noise and in most BER scenarios it is a better indication of
good signals plus it is insensitive to signal amplitude.
The metric for choosing the best antenna is determined by
CR5 bit 3. When set to a zero the antenna with the smallest
phase variance (SQ2) is chosen. This metric has shown to
have a poor measure of multipath effects and is best suited
for 1MBPS and 2MBPS operations. When set to a one, the
six sidelobes (3 on either side of the 3 centered on the bit
sync peak) are summed and compared. The antenna with
the smallest sum (SQ3) is selected. This metric is optimal for
improving 5.5 and 11MBPS operation in the presence of
multipath.
CR5 bit 4 is to select the bit sync accumulation duration
used during antenna dwells. When set to a zero the
accumulation is over 15 symbols (consistent with HSP3824,
HFA3824A, HFA3860). This setting allows the user to set the
CSE and SQ1 thresholds as before and retain consistent
CSE and acquisition performance. When set to a one, the bit
sync accumulates on the last 13 symbols instead of the last
15. The SQ1 value will be numerically smaller, so CSE and
SQ1 acquisition thresholds may need adjustment. The
benefit of setting this bit is the elimination of transients (due
to antenna switching and A/D timing adjustments) in the bit
sync accumulation. This provides the best possible data for
SQ3 based antenna diversity.
The bit sync amplitude and phase noise are integrated over
each block of 16 symbols used in acquisition or over blocks of
64 symbols in the data demodulation mode. The bit sync
amplitude measurement represents the peak of the
correlation out of the PN correlator. Figure 14 shows the
correlation process. The signal is sampled at twice the chip
rate (i.e., 22MSPS). The one sample that falls closest to the
peak is used for a bit sync amplitude sample for each symbol.
This sample is called the on-time sample. High bit sync
amplitude means a good signal. The early and late samples
are the two adjacent samples and are used for tracking.
The other signal quality measurement is based on phase
noise and that is taken by sampling the correlator output at
the correlator peaks. The phase changes due to scrambling
are removed by differential demodulation during initial
acquisition. Then the phase, the phase rate and the phase
variance are measured and integrated for 16 symbols. The
phase variance is used for the phase noise signal quality
measure (SQ2). Low phase noise means a stronger
received signal.
Procedure to Set Acq. Signal Quality Parameters
Example
: There are four registers that set the acquisition
signal quality thresholds, they are: CR 8, 9, 10, and 11
(RX_SQX_IN_ACQ). Each threshold consists of two bytes,
high and low that hold a 16-bit number.
These two thresholds, bit sync amplitude CR (8 and 9) and
phase error CR (10 and 11) are used to determine if the
desired signal is present. If the thresholds are set too “low”,
that increases the probability of missing a high signal to
noise detection due to being busy processing a false alarm.
If they are set too “high”, that increases the probability of
missing a low signal to noise detection. For the bit sync
amplitude, “high” actually means high amplitude while for
phase noise “high” means low noise or high SNR.
A recommended procedure is to set these thresholds
individually optimizing each one of them to the same false
alarm rate with no desired signal present. Only the background
environmentshouldbepresent,usuallyadditivegaussianwhite
noise (AGWN). When programming each threshold, the other
threshold is set so that it always indicates that the signal is
present. Set register CR8 to 00h while trying to determine the
valueofthephaseerrorsignalqualitythresholdforregistersCR
10 and 11. Set register CR10 to FFh while trying to determine
the value of the Bit sync amplitude signal quality threshold for
registers 8 and 9. Monitor the Carrier Sense (CRS) output
(TEST 6, pin 45) in test mode 1 and adjust the threshold to
produce the desired rate of false detections. CRS indicates
valid initial PN acquisition. After both thresholds are
programmed in the device the CRS rate is a logic “and” of both
signal qualities rate of occurrence over their respective
thresholds and will therefore be much lower than either.
PN Correlators Description
There are two types of correlators in the HFA3860A baseband
processor. The first is a parallel matched correlator that
correlates for the Barker sequence used in preamble, header,
and PSK data modes. This PN correlator is designed to
handle BPSK spreading with carrier offsets up to
±
50ppm and
11 chips per symbol. Since the spreading is BPSK, the
correlator is implemented with two real correlators, one for the
I and one for the Q Channel. The same Barker sequence is
always used for both I and Q correlators.
These correlators are time invariant matched filters otherwise
known as parallel correlators. They use one sample per chip for
correlation although two samples per chip are processed. The
correlator despreads the samples from the chip rate back to the
originaldatarategiving10.4dBprocessinggainfor11chipsper
bit. While despreading the desired signal, the correlator
spreads the energy of any non correlating interfering signal.
The second form of correlator is the serial correlator bank used
for detection of the MBOK modulation. There is a bank of eight
8 chip correlators for the I Channel and another 8 for the Q
Channel. These correlators integrate over the symbol and are
HFA3860A
相关PDF资料 |
PDF描述 |
|---|---|
| HFA3860A | Direct Sequence Spread Spectrum Baseband |
| HFA3860AIV | 3.3V 288-mc CPLD |
| HFA3861AIN96 | Circular Connector; No. of Contacts:21; Series:MS27473; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:22; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:22-21 RoHS Compliant: No |
| HFA3861AIN | 288 MACROCELL 3.3 VOLT ISP CPLD |
| HFA3863IN | Direct Sequence Spread Spectrum Baseband Processor |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HFA3860B | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:nullDirect Sequence Spread Spectrum Baseband Processor |
| HFA3860BIV | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA3860BIV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3860BIV96 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA3860IV | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
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